News Article

Etching And Regrowth Technique Increases Bipolar Diode Stability

The lack of forward voltage stability in SiC bipolar devices is hampering their deployment in electrical power transformers. However, this problem can be overcome with an etching and regrowth process, say Joe Sumakeris, Brett Hull and Dave Grider from US chip manufacturer Cree.

The improved switching efficiencies of high-voltage SiC discrete power devices have the potential to deliver significant energy and space savings in AC-DC power converters deployed in civilian infrastructure and in military vessels. But to fulfill these applications multi-kV SiC devices are desired to be run in bipolar conductivity mode for increased current density. Unfortunately this can lead to a forward voltage (Vf) drift under conductivity modulation, according to studies carried out by us and other researchers. The problem is so significant that it drove some companies to abandon pursuing this device technology.



The Vf drift stems from the propagation of basal plane dislocations (BPDs) that exist in the SiC substrate into the epilayer. Here, they are converted into Shockley stacking faults when the device is operated in bipolar conductivity mode. In vertical power devices, where current flow is essentially perpendicular to the basal plane, these stacking faults trap carriers and dramatically increase the device s resistance.

To combat the Vf drift we have developed specific techniques for substrate preparation, epilayer growth and device fabrication (see figure 1). This enables us to reduce the number of BPDs in the parts of the device that experience conductivity modulation and produce stable, multi-kV bipolar power devices. We believe that this approach, which relies on substrate preparation and epilayer regrowth, represents the greatest recent advance in bipolar SiC device technology.



We started developing methods for reducing the Vf drift about six years ago. Our first incremental improvements in stability came by restricting the electron-hole plasma to regions of devices with fewer BPDs. By 2003 we had modified our PIN devices to include a thick, heavily doped n-type buffer layer between the substrate and the drift layer, and a relatively thick anode layer on top of the drift layer. The buffer layer isolates the electron-hole plasma from the BPDs in the substrate, while the anode layer separates the plasma from the ohmic regions and protects the drift layer from any mechanical damage that can occur during processing. Re-introduction of BPDs at growth interruptions is prevented by growing the modulated portion of the structure in a single uninterrupted step.

Although these steps are beneficial, most of the drift-inducing BPDs come from the substrate and propagate into and through the epilayers. If these BPDs could be eliminated from the substrates, this would improve device stability. However, this is an extremely long-term goal and instead we currently have to contend with the BPD densities of 104–105 cm–2 that exist in commercial substrates.

An alternative approach for increasing device stability involves the growth of a strained layer that can block and redirect the BPDs. This approach has already been applied to the GaAsP/GaAs material system, where it was used to prevent the propagation of threading dislocations. However, it is not clear whether strained layers will have the same effect on BPDs in SiC and any efforts to develop this technology will be hampered by the lack of published information concerning the formation of SiC-compatible strained layers.

Making better defects

Device stability can also be improved by converting these BPDs into other forms of defects that cause fewer problems. Thankfully, this process can actually occur both naturally and efficiently during epitaxial growth, with BPDs being transformed into threading edge dislocations (TEDs) that have less impact on device performance (see figure 2). Normally more than 90% of the substrate BPDs will naturally convert to TEDs during epilayer growth, which cuts the typical epilayer BPD density to 300 cm–2. On its own this natural reduction in BPD density is insufficient for the fabrication of commercially relevant SiC power devices. However, improving the efficiency of the natural BPD–TED conversion appears to offer the most promising solution.



Mark Skowronski from Carnegie Mellon University, PA, has suggested that a reduction in dislocation length can boost the subsequent conversion of BPDs into TEDs during epilayer growth. TEDs are preferred to BPDs because they are shorter and consequently produce a smaller increase in the system s overall energy.

In SiC substrates the BPDs exist in many different directions, while in epilayers they predominantly occur in one particular direction, which is determined by the substrate s off-axis angle and orientation. For typical 8° off-axis material, the length of a substrate BPD that propagates into the epilayer without undergoing any transformation is roughly seven times that of a BPD that is converted to a TED during epilayer growth. Reducing the off-axis angle of the SiC substrate can increase this disparity and potentially enhance the dislocation conversion process. However, this approach also has its drawbacks and leads to poorer quality surfaces with higher overall defect densities.

Our new etching approach



Selective etching can be used to locally reduce the off-axis angle in the immediate vicinity of a BPD while maintaining a more favorable off-axis angle for the majority of the substrate (see "The benefits of selective etching"). In this process, the SiC substrate is selectively etched before a BPD conversion epilayer is deposited (see figure 1). The epilayer surface is then repolished to recover a smooth, pit-free surface for growth of the actual device structure.

To evaluate the benefits of our new process, we grew a batch of epiwafers on which we fabricated 10 kV, 20 A PIN diodes. Seven wafers were produced with low-BPD processing, along with one control wafer that did not have any low-BPD processing. The Vf stability of the diodes was evaluated by comparing the change in Vf after 100 A/cm2 was passed through the on-wafer devices for 30 minutes (see figure 3). The pass mark was set at a drift of less than 0.1 V.



The results show that 51.3% of the diodes fabricated on low-BPD wafers had a stable Vf. In contrast, none of the diodes fabricated on the unprocessed substrate exhibited forward-voltage stability and 80% of the devices drifted by more than 2 V.

Clearly, this low-BPD technology delivers a substantial improvement in bipolar SiC device s Vf stability and brings us closer to a commercially viable product. However, the low BPD conversion process is cumbersome and costly, the yields need to be improved, and there are several issues to be resolved before this process is ready for production.

First, the current process needs to be shortened and simplified, but this should be possible because we are currently using conservative conditions for pre-etch, regrowth and polish. In fact, we expect that as the quality of each stage is improved the overall process will become much more manageable. Second, we must continue to reduce the defect density in low-BPD material, as this will increase the overall device yield. Even with an intermediate repolishing step, the legacy of the selective etch process contributes to higher defect densities in the device epilayers. Last, we have to confirm the long-term reliability of low-BPD material. While the 30 minute stress test provides a convenient metric, it fails to deliver the rigor required to ensure that the devices are stable throughout a typical service life.

If we are able to address these three issues, we will be in a position to manufacture stable, high-voltage SiC PIN diodes that can deliver significant energy savings for power conversion.

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