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Calculations unveil two problems with the Auger theory for LED droop. This recombination mechanism is far too weak, and it has a temperature dependence that fails to tally with experimental results
UCSB achieves sub-300 nm emission using AlN base layers

The growth of UV emitters on AlN buffer layers on sapphire substrates is the subject of much research because AlN films are transparent down to 200 nm and provide a good lattice and thermal expansion match to the AlGaN active layers. Amy Hanlon and colleagues at the University of California, Santa Barbara (UCSB) have reported the first sub-300 nm electroluminescence from devices grown on an AlN base layer on a sapphire substrate (Jpn. J. Appl. Phys. 42 (Pt.2 (6B)) L628).

First, an AlN nucleation layer was deposited on the sapphire at 700 °C, using a low V/III ratio. The reactor temperature was then raised to 1150 °C, and a 0.67 µm AlN base epilayer was deposited. The H2 carrier gas flow was found to be very important for film quality, with improved surface morphology achieved at 10 slpm H2 (figure 1).

Using an AlN base epilayer, the team was able to grow crack-free AlxGa1-xN films with an Al mole fraction of 0.30-0.99. The AlGaN film composition was strongly dependent on both temperature and ammonia flow. No superlattices were used for strain relief, dislocation filtering, or improved doping, with the 0.67 µm of AlN serving as the base epilayer, followed by 0.75 µm of Si-doped n-Al0.7Ga0.3N. The single quantum well was approximately 6 nm of Al0.4Ga0.6N and was capped with 0.1 µm of Mg-doped p-Al0.4Ga0.6N. The final layer was p++GaN grown at atmospheric pressure to just 20 nm thick to avoid extensive absorption of emitted UV light. For unpackaged devices tested on wafer at a continuous current of 120 mA, an optical power of 2.4 µW was achieved. Peak emission was 292 nm, with very little secondary wavelength emission.

AmberWave demonstrates SiGe-free SSOI

Strained Si and silicon-on-insulator (SOI) technologies are already considered viable technologies for mainstream silicon industry adoption and are extending the performance of Si CMOS microelectronics (Compound Semiconductor September 2002). While each technology separately provides advantages that result in increased chip speed and decreased power consumption, the combination of the two technologies, strained silicon on insulator (SSOI), provides the additive benefits of both technologies. SSOI, potentially more than the sum of its component technologies, promises to define the future of the silicon industry roadmap.

Researchers at AmberWave Systems in Salem, NH, have demonstrated a SiGe-free SSOI substrate technology, as well as describing a method of verifying strain levels in SiGe-free SSOI (Appl. Phys. Lett. 82(24) 4256). The SiGe-free SSOI substrates were fabricated by wafer bonding and hydrogen-induced layer transfer of strained Si grown on bulk relaxed SiGe graded layers followed by selective removal of the transferred SiGe layer. The crucial steps were fabrication of the initial high quality bulk strained Si substrates with low surface roughness and selective SiGe removal by low-temperature wet oxidation and an oxide etch. This method enables the fabrication of well controlled, epitaxially-defined, thin strained Si layers directly on an insulator layer compatible with the sub-200 Å Si film thickness requirements for fully depleted device technology.

Tensile strain levels of 1.15-1.26% were been verified in these structures by Raman spectroscopy and X-ray diffraction, and were not subsequently diminished by moderate thermal budget processing. The strain in the structure was thermally stable during 1000 ºC tube anneals for at least three minutes. The strain-inducing relaxed SiGe layer is not present in the final structure, eliminating some of the key implementation challenges inherent to other SiGe-on-insulator-based solutions. The process used and structure achieved in this demonstration are critical steps towards the commercialization of SSOI as an ideal platform for future generations of Si-based microelectronics.



New record set for bonded VCSELs

Considerable debate over cost, yield and performance has surrounded the techniques for producing long-wavelength VCSELs. Wafer bonding can be used to integrate InP active regions which are epitaxially incompatible with GaAs-based DBRs. Alternatively, GaInNAs active regions can be grown directly onto AlGaAs/GaAs DBRs. Although the recently announced first mass-produced 1310 nm VCSELs use a dilute nitride active region, the supporters of the wafer bonding approach cite performance benefits of using an InP active region, such as greater wavelength flexibility and higher gain compared to GaInNAs active regions.

In a late-news paper at June’s CLEO meeting in Baltimore, MD, John Bowers and colleagues from UCSB revealed details of a VCSEL structure, which has taken bonded VCSELs to new levels of performance. The active region contained five AlInGaAs QWs grown onto an n-InP bottom contact. On top of the active region is an InAlAs/InP tunnel junction buried beneath a regrown n-InP contact layer. The top and bottom mirrors were bonded to the contact layers (figure 2). At a wavelength of 1335 nm, the single mode output power was 1 mW when operating at 80ºC. The authors say that this is the highest power reported to date at this temperature for a long-wavelength VCSEL. At room temperature, 2 mW was achieved and the device operated at up to 134 ºC.


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Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

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Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

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