News Article

High-k Gate Stacks Point Towards Digital Convergence

Despite the recent application of high-k dielectrics and metal gates in volume CMOS processes, and the scattergun approach to logic devices based on III–V materials, the compound and silicon industries have much in common. Bob Metzger looks at post-CMOS convergence.

Some in the III–V world may have taken recent news from Intel and IBM about their individual developments of highly insulating materials (high-k dielectrics) and metal gates in place of SiO2 as bad news for digital applications of GaAs. On the face of it, it might have seemed that compound efforts could become redundant if CMOS is able to continue scaling.

But those who have been working with III–Vs for digital IC applications are quick to disagree. Jesus del Alamo at MIT, who has been investigating the use of AlInAs/InGaAs HEMTs on InP for digital IC applications, said: "The announcements from Intel and IBM are not entirely unexpected. It was clear that high-k dielectrics would eventually show up, and this does not really change things. The current view is that silicon will run out of steam around the 22 nm node [post-2011] and that new materials will be required."

It isn t just the III–V specialists saying this. Robert Chau is the director of transistor research and nanotechnology at Intel, and as one of the central players in this area, he already needs to look at integrating more and more non-silicon technologies. Chau sees III–Vs as one of the first of the possible successor technologies to be integrated onto the existing silicon platform. He shares the view that the recent development of high-k dielectrics and metal gates in Intel s CMOS process will not have a negative impact on the development of III–Vs for digital circuits. In fact, he believes the opposite: "The recent Intel breakthrough in high-k/metal-gate research on silicon and its successful implementation in Intel s 45 nm processor products should and will have a positive impact on high-k research for III–Vs."

The big problem with III–V logic also centers on the gate material, but it is more fundamental. Fabricating a gallium-based oxide compatible with volume production has proved to be an unsurmountable problem thus far.

Chau said: "The research on high-k gate dielectrics on III–Vs has been ongoing for many years. Currently, III–V transistors still do not have a compatible gate dielectric and they suffer from high Schottky gate leakage. Eventually III–V CMOS transistors will need a reliable high-k gate dielectric to eliminate such leakage for low-power applications."
The silicon challenge

So, it seems that III–Vs do have a digital future. But, before one can evaluate the applicability of digital GaAs transistors to real-world applications, it is important to understand what silicon is capable of.

The paradigm shift to high-k dielectrics was forced by limitations inherent in the SiO2 gate oxide. With gate lengths scaled down to the 60–70 nm range, gate oxides just 1.2 nm thick are required. But further scaling is a problem: any thinner, and the oxides simply do not stand up against the operational gate voltages and leakage current becomes excessive. As a result, the International Technology Roadmap for Semiconductors (ITRS) stipulates that, to get around this problem for the 45 nm production node, a high-k dielectric must permit the use of a thicker layer to hold off gate voltages, but also have an "effective oxide thickness" (EOT) thinner than 1.2 nm to meet performance requirements.

Both IBM and Intel have chosen HfO, which has a dielectric constant approximately six times that of SiO2, for this gate insulation. Transmission electron microscopy images of the oxide/semiconductor interface suggest that their new devices use 2–3 nm HfO layers – yielding an EOT well below 1.0 nm. These new transistors also require an alternative to the polysilicon gates normally used. This is because a polysilicon/high-k dielectric interface results in a pinned Fermi level (EF), while it also degrades channel mobility due to coupling between the high-k dielectric and the inversion charge in the channel. Intel is using individual metal gates for the PMOS and NMOS (p-channel and n-channel) devices to solve this problem. Those metals, whose exact compositions remain a secret, can be used to adjust individual threshold voltages.

When compared with the prior generation of polysilicon/SiO2 transistors, the new materials improve drive current by 20% and reduce source-drain leakage current by a factor of five. They will be used in the quad-core version of Intel s next-generation "Penryn" processor, which will contain 800 million transistors.

One can make an educated guess as to how this device may evolve. Biaxially-strained active silicon layers on top of a relaxed SiGe layer could be employed to alter bandstructure and improve mobility, for instance. But even if such a device is pushed to its theoretical limit, the ITRS forecasts that when gate dimensions reach 14 nm, CMOS will hit a fundamental technology roadblock. This is expected around the year 2020.
The III–V opportunity

So, if this is where the opportunity for III–V logic lies, what are the realistic options and what has been achieved so far? To answer those questions, we need to take a close look at some of the fundamental concepts that underpin all digital electronics.

Transistors can be operated in either enhancement mode (E-mode) or depletion mode (D-mode). An E-mode device requires a gate voltage to be turned on. D-mode transistors are naturally "on" and are switched off by a gate voltage (see figure 1).

For many, the E-mode NMOS device is synonymous with the formation of an inversion layer. From a more fundamental perspective, it is simply a device that turns on with a positive applied voltage. This may seem trivial, but the distinction is critical when considering the various E-mode III–V-based devices under development for digital applications.

For silicon, high-quality SiO2 permits both NMOS and PMOS type devices – the two fundamental building blocks of digital circuitry. The key is that the NMOS and PMOS devices can be combined in the fabrication of fast, efficient ICs through CMOS processing.

Unfortunately, the lack of a high-quality, native III–V oxide has seriously hampered logic transistor development in GaAs. It has limited the fabrication of rectifying junctions to p–n and Schottky junctions only. As a result, the typical digital GaAs device is the MESFET, in which the gate is formed by a rectifying Schottky metal-semiconductor junction. While able to hold off significant reverse biases, this junction will pass significant currents at small forward biases. This property limits the implementation of MESFETs in logic applications to small (500 mV) voltage swings dictated by the Schottky gate structure. Although very fast MESFET logic has been developed, the approach requires complex layouts and consumes excess power.

This inherent weakness, in particular for E-mode n-channel devices, has driven the search for a compatible oxide that would eliminate the need for Schottky junctions and allow fabrication of a true III–V CMOS hybrid. Until recently, that search had been largely fruitless, and even today the best of these devices remain at the early research stage.

Researchers from Kanazawa University in Japan obtained one of the best results in 2004. They formed an oxi-nitride gate dielectric using ozone oxidation and a nitrogen gas plasma. The result was an n-channel E-mode GaAs MOSFET with a threshold voltage of 0 V and a claimed transconductance of 50 mS/mm (see Tametou et al. 2004). It represented a major breakthrough for inversion-mode GaAs MOSFETs, because the transconductance was nearly two orders of magnitude greater than anything previously reported. While impressive, this transconductance figure remains significantly lower than that of a basic NMOS device.

Fortunately, there is another path to making E-mode MOSFETs in GaAs – one that does not rely on the generation of an inversion charge at the semiconductor–dielectric interface.

Led by Matthias Passlack, researchers at Freescale Semiconductor have developed a non-inversion-type E-mode MOSFET – in other words, a MOS-PHEMT hybrid (see figure 2 for the epilayer design and the bandstructure). In this approach, the epilayers beneath the MOS portion of the device form an InGaAs strained channel (see Passlack et al. 2006 and 2007). The transistor dielectric consists of an amorphous layer of Ga2O3/GdGaO. The Ga2O3, which sits at the semiconductor–dielectric interface, is just three or four monolayers thick, and GdGaO forms the remainder of the high-k dielectric. With a dielectric constant of 20, GdGaO behaves like a thinner version of SiO2.

Unlike a conventional PHEMT, where threshold voltage is set by the depth of the gate recess etch, in the MOS-PHEMT hybrid this property is determined by the thickness of the dielectric layer and its distance from the channel, as well as the gate metal work-function. The geometry of the gate and the underlying epilayers also distance the channel from the semiconductor–dielectric interface (see figure 3).

In collaboration with researchers at the Nanoelectronics Research Centre (now the James Watt Nanofabrication Centre) at the University of Glasgow in the UK, Freescale fabricated E-mode devices with 1 μm gate-lengths and dielectric layers ranging from 10 to 18 nm thick. The resulting transistors had a threshold voltage of 0.28 V, a maximum drain current of 397 mA/mm and a maximum transconductance of 428 mS/mm.

Although they are an order of magnitude better than the Japanese group s GaAs MOSFETs, these results are close to what one would expect for a GaAs PHEMT utilizing a similar channel structure. At first glance, therefore, this device might be viewed almost as a regular PHEMT – albeit one in which the threshold voltage is dictated by the geometry of the dielectric layer rather than the depth of the recess etch. However, the Ga2O3/GdGaO dielectric has done more than simply set the threshold voltage: it has eliminated the problematic metal-gate Schottky layer.

Now, let s take a closer look at the InGaAs/InP devices that Jesus del Alamo and his MIT team have been working on, which, at first, appeared to highlight a rather different approach. Although these devices scale well to gate lengths of 100 nm, serious short-channel effects then begin to appear – including shifts in threshold voltage as a function of gate length, and drain-induced barrier lowering. However, these effects can be reduced dramatically by thinning the AlInAs Schottky layer to 3.0 nm, making 50–60 nm gate-length devices perfectly feasible.

But – just like SiO2 – AlInAs Schottky layers less than 3 nm thick begin to exhibit excessive leakage. Drain currents become dominated by charge passing from the gate into the channel, and the transistors become useless. "This is the key limitation for scaling and the need for a high-k dielectric to allow future scaling is very clear," said del Alamo. The solution, and the future device that he envisages is, in fact, of the same type as Freescale s – the hybrid MOS-PHEMT.

Intel not only sponsors del Alamo s work – it is actively involved in the development of even more exotic III–V devices and potential dielectrics for digital applications. Working with Qinetiq in Malvern, UK, its researchers have fabricated 85 nm InSb channel PHEMTs in both E-mode and D-mode form, where the threshold voltage is determined by the depth of the recess etch (see Datta et al. 2005 and Chau 2006).

The InSb material system exhibits the highest electron mobility and saturation velocity of any known semiconductor, and Intel is aiming to develop a future generation of very-low-power logic devices with a VDS of only 0.5 V. Chau and his researchers are also investigating possible dielectrics to replace the Schottky gate, and they have found that Al2O3 can reduce gate leakage into the channel by six orders of magnitude.

What all of this work is pointing to is an increasing convergence of approaches to find the best digital IC platform for a post-CMOS industry. Whether research teams are focused on III–V or silicon, all are envisioning a device that merges the best of both worlds. In other words: a channel region taking advantage of the superior transport characteristics of high mobility III–V materials, combined with a metal-gate/high-k dielectric to allow device scaling well into the sub-50 nm region.

Efforts to optimize the pairing of high-k gate dielectrics with the underlying semiconductor will now begin, with teams seeking combinations that will minimize the number of traps and defects at the semiconductor interface and the negative interaction with charge in the channel, while maintaining low gate-leakage currents.

MBE specialist David Braddock, CEO of OSEMI in Rochester, supplied the initial Ga2O3/GdGaO dielectric stacks on GaAs to Freescale. He sees the common ground between this approach and the efforts at MIT, Intel and elsewhere. "High-k dielectric gate stacks for compound semiconductors is the real enabling technology," he said.

But when Braddock looks at this convergence, his compound material of choice is different again. Alongside Mark Johnson and Doug Barlage at North Carolina State University, Braddock has considered the nitride system as a strong candidate for merging with high-k dielectrics. According to him: "In the case of GaN, gallium oxides may be mixed with hafnium and gadolinium oxides to form strained oxide layers with low border trap densities and low interface state densities."

Although precisely which III–V materials and high-k dielectrics will end up being used remains an open question, a common vision is beginning to emerge – one shared by key figures in both III–V and silicon. It is a convergence of the best of both worlds that will carry digital ICs beyond the CMOS era.

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