Info
Info
News Article

Printing Cuts The Cost Of Uniting III-Vs With Silicon CMOS

Semprius is refining and scaling a versatile printing process for uniting III-Vs with silicon. The technique will cut the cost of photovoltaics and RF and broadband sources, say Kyle Benkendorfer, Etienne Menard and Joseph Carr.
A lot of time has been devoted to the tricky problem of combining the best attributes of compound semiconductors, like high mobility and a direct bandgap, with the low-cost, mature manufacturing processes of silicon CMOS. The efforts have brought success at the research level, but in many cases commercialization is still a distant dream.




One technique that does promise near-term commercialization, however, is a simple, scalable process for the heterogeneous integration of III-Vs and silicon. This process was invented at the University of Illinois, Urbana-Champaign, by John Rogers and his team. The technique, which can create unique architectures that will ultimately produce new high-performance, low-cost RF and broadband devices and high-spectral-response photovoltaics, is being licensed by us at Semprius, a spin-out based in Durham, NC (see "The Semprius story so far" for more details about the company). We plan to refine this process for volume production and ultimately commercialize the technology over the next few years.



Our technology centers on a printing technique for transferring sub-millimeter sized, sub-micron thick "chiplets" – which could include individual compound semiconductor transistors or small circuits – from one substrate to another (see figure 1). With an elastomeric stamp, arrays of chiplets can be transferred from donor to acceptor substrates in a single process.

The process begins by bringing a stamp into intimate contact with chiplets formed at the surface of compound semiconductor wafers (see figure 1 (b)). This stamp is then peeled back at a rate that removes the microstructures efficiently from the donor substrate, while maintaining their order and alignment (see figure 1 (c)). These chiplets are then printed onto the target substrate, which has been coated with an ultrathin film adhesive, and the stamp is peeled back ensuring full transfer of the microstructures.




Before this process can begin, the chiplet s dimensions are defined with a "delineation" process. This step involves using an etchant to produce streets around the chiplets and remove a release layer. The undercutting process can be applied to GaAs wafers with AlAs release layers and to GaN films grown on silicon (111) substrates – an orientation that is suitable for GaN growth, but not CMOS processing. When the underlying silicon is etched, "microbridges" are formed that hold the chiplets in place before they are transferred to CMOS-compatible silicon (100) (see figure 2 (b)).

Our printing process has already printed single-crystal silicon, GaN and GaAs chiplets with thicknesses of 50 nm–100 Âµm and lateral dimensions ranging from 300 nm to a few millimeters. Examples include a 30 mm × 38 mm array of 24,000 silicon microstructures on a 100 mm GaAs wafer, which was produced with a process yield – including micromachining, pick up and release – of 95% (see figure 2 (c) and (d)). A reverse approach is possible, involving the printing of GaAs ribbons onto a silicon surface. We have successfully created many other structures with this approach, including silicon MOSFETs and GaN MESFETs arrays, circuits featuring ring oscillators, differential amplifiers, logic gates, diodes and resistors – which have been interconnected to the underlying substrate using evaporated metal lines formed over the device s edge.

Our work has not been limited to the transfer of chiplets onto silicon and GaAs substrates: we have also developed this technique for transfer onto flexible plastics. On these platforms we have proven that printing does not dramatically alter device performance. Silicon chips on polyimide show mobilities of over 400 cm2/Vs and on/off ratios of over 106, and GaAs transistors on polyethylene terephthalate produce typical I-V characteristics.

A key feature of our printing approach is the isolation of demanding fabrication processes to specific mother substrates. This means that different optimized and tailor-made processes can be applied to the compound semiconductor chiplets and the receiving CMOS silicon wafer in the most efficient and affordable way. Complications from incompatible or inefficient processes are avoided.

The transfer printing step also delivers two major benefits: massively parallel transfer of chiplets and "geometric magnification." Depending on the specific circuit configuration, each transfer step can print between hundreds and tens of thousands of chiplets simultaneously, which cuts costs and boosts manufacturing throughput. By designing the silicone stamp pad to pick up only one of every "n" chiplets, the printed substrate can also be populated over a larger area using a less dense array. On return to the source, the stamp can be indexed over one chiplet and the process repeated, thereby ensuring a very efficient use of the chiplets.

Another advantage of our process is that it can affordably handle and print chiplets with lateral dimensions of just 10 μm, whereas traditional methods typically struggle to handle die with sides below 100 μm. The etching step is also cheaper than dicing-based methods, which waste more material and produce less devices per wafer.
Printing challenges




The primary challenge is to place the chiplets with enough accuracy. The elastomeric stamps used to do this are made by casting and curing a 1 cm thick piece of silicone rubber against a master substrate. They are capable of replicating the master s nanometer-scale patterns, so long as the stamp is made from a low-modulus silicone such as polydimethylsiloxane. However, single-layer stamps built with this soft material are prone to deformation during printing, which limits their use to coarse placement. Fortunately, this weakness can be addressed with advanced composite stamps that have low coefficients of thermal expansion, high in-plane mechanical rigidity and environmental stability, and a placement accuracy of less than ±2 μm (see figure 3).

The printing technique must also be compatible with the brittle chiplets. This brittleness stems from the fully fabricated chip s structure, which has several dielectric and metal layers on top of the thin epitaxial layer. These additional layers have a built-in strain that causes the ultrathin chiplets to bow after the wet-etching undercut process. However, this bowing can be avoided by optimizing the shape of the micro-bridge structures, so that they maintain the chiplet s flatness when they are attached to the wafer. Alternatively, the chiplet s mechanical stress can be offset with strain-balanced passivation layers.




Ours is not the only technique under commercial development for marrying silicon s cost and processing advantages with high-performance compound semiconductors. However, we believe that our approach has greater flexibility than alternative methods, which require improvements to silicon s performance, techniques to grow III-Vs directly onto silicon and wafer-to-wafer technologies (see box "Rival approaches to integration").

One market that could benefit from our approach to circuit production is GaAs power-module manufacture. Discussions with several component makers and cost models produced by an industry expert have revealed that our printing approach could lead to cost savings through more effective use of GaAs and silicon. These savings result from using GaAs to make the transistors and the silicon CMOS substrate to form other components in the circuit, such as resistors and capacitors. This cuts the compound semiconductor real estate for each power-amplifier module and enables the costs of these units to approach CMOS silicon levels.

We are also targeting high-efficiency, high-spectral-response photovoltaics. Printing techniques can cut the production costs for these devices because an optimized combination of different materials can be brought together that offers high performance at low cost. Our process also offers further savings through wafer reprocessing, because our street etch process only removes a few microns of material.

We are now working to scale up a robust printing process to address both of these markets, and also markets involving active matrix display backplanes, large-area sensor arrays, such as X-ray detectors, and flexible electronics, such as smart packaging and RFID tags. We are also developing partnerships with companies that are expert in certain target markets and we are keen to engage more partners. We expect that our technology will be commercialized in the next few years.



AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.

REGISTER FOR FREE

VIEW SESSIONS

Info
×
Search the news archive

To close this popup you can press escape or click the close icon.
×
Logo
×
Register - Step 1

You may choose to subscribe to the Compound Semiconductor Magazine, the Compound Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
 
X
Info
X
Info
{taasPodcastNotification}
Live Event