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III-Vs And CMOS: The Logical Choice?

Traditionally the conference where future silicon processes first emerge, it was standing room only for "III-V CMOS" at the 2007 International Electron Devices Meeting held in Washington, DC.

If you want to peek at the future of silicon CMOS processing, the International Electron Devices Meeting (IEDM) is the place to start. Alternating between Washington, DC, and San Francisco each December, and running for more than 50 years, it is where key semiconductor technologies often emerge.

The researchers in attendance are facing what some are calling the greatest problem in microelectronics technology in a generation – finding a replacement for silicon logic.

At the 2007 event in Washington, compound semiconductors were making their biggest impression yet on the CMOS research community. While Intel s presentation on its commercial implementation of high-k gate dielectrics drew much attention, the atmosphere in a tiny conference room crackled with anticipation as the same company presented details of GaAs-on-silicon epitaxy that has produced a defect free quantum-well transistor.

Although many view Intel as a company apart within the wider CMOS community, there was evidence to suggest that compound materials will play a significant role in the future – perhaps by 2015.

Eight years might seem a long way off, but the semiconductor industry roadmap demands that a solution is "on the table" in just three years. Jesus del Alamo from the Massachusetts Institute of Technology (MIT) was chairman of the compound semiconductor subcommittee at IEDM. After the event he said that the conference was notable for the upsurge in attention now paid to III-V CMOS.

"There was definitely much more interest this year than in previous years," said del Alamo. "The concept of III-V CMOS started being mentioned at IEDM in 2005 through a couple of papers. In 2006 we had some intriguing papers that suggested significant promise. In 2007 we saw a lot of good work and serious debate. There is no question that this is a hot topic now."

IEDM 2007 kicked off with a Sematech workshop entitled "III-V CMOS on Silicon: Technical and Manufacturing Needs". Convened by Robert Chau – Intel s director of transistor research – the Aixtron-sponsored workshop drew a small but keen band of attendees, who decided that the scalability of MOCVD makes it the most promising manufacturing approach. And while InGaAs is the leading candidate for channel material, dual-channel devices may feature germanium in the PMOS structure.

Chau was part of the team that worked with IQE s Bethlehem, PA, operation on the new GaAs-on-silicon transistor. It appears to have overcome a key problem – the huge lattice mismatch between these two materials – to produce active quantum-well device layers that are virtually defect free.

Chau and his team did that by forming a composite InAlAs buffer layer to "filter out" the defects and stop them extending into the quantum wells. Although this has been done before, the Intel and IQE researchers have been able to reduce the thickness of this buffer layer, deposited using MBE, to 1.3 µm.

The enhancement mode quantum-well transistor (QWFET) it then fabricated, which featured an 80 nm gate, had a much higher cut-off frequency than standard 60 nm gate silicon n-MOSFETs. That additional speed could be exploited directly in logic circuits or, if it operated at the same speed as the all-silicon device, the QWFET would allow a 10-fold reduction in DC power dissipation.

However, despite this and other promising research at IBM, Freescale and the University of Glasgow, many remain unconvinced by the Intel work and there is a big divide among the III-V proponents and the nay-sayers. "By 2012 we should have a real working solution for III-V," suggested Chau, while others in the industry argue that the sheer number of technical issues that still need to be addressed would make the complexities of III-V CMOS impossible to resolve fully in time for devices at the 22 nm node. Scaling up to 12 inch wafers and switching to MOCVD deposition are just two of the key goals, and there are some fundamental question marks over the Intel device – like how to switch it off.

That split was also reflected in a packed panel session hosted by Dimitri Antoniadis from MIT, in which he asked the audience whether looking beyond silicon in logic applications would remain a pipe dream, or whether it really is the inevitable next step in CMOS evolution.

By the end of that discussion around half of the audience said that, aside from gate structures, they believed that non-silicon materials would feature in CMOS by 2020 – hardly a ringing endorsement of the approach, but a more favorable proportion than you could have expected just a couple of years ago. Del Alamo certainly thought so: "There is a rapid change of opinion on this topic, as the difficulties for further silicon scaling become more obvious."

"A couple of years ago, it was nearly a ridiculous idea to entertain the notion of III-V CMOS," he added. "Today, it s no longer ridiculous. The topic is being seriously debated."

As the guest luncheon speaker at IEDM 2007, TSMC chairman and CMOS industry veteran Morris Chang listed what he called the six disruptive developments that have shaped the business over the last 40 years: first the transistor; then the integrated circuit; Moore s Law; CMOS itself; the microprocessor; and – unsurprisingly – the foundry-based manufacturing business model.

High-k gate dielectrics might be the next breakthrough to be added, and it would certainly be premature to include III-V materials on such a list any time soon. But, given the upsurge in attention that a growing element of the mainstream CMOS community is now paying compound materials, IEDM 2007 could eventually come to mark a watershed moment for the semiconductor industry.

For that to happen will require far more involvement from semiconductor manufacturers outside Intel and IBM. Del Alamo believes that the recent upsurge of interest in III-V CMOS is largely due to these two companies, but also that much more is needed. "Everybody else is sitting on the fence," he said. "[But] the challenges that this technology faces are enormous. We need more people to be engaged and we need more collaboration and coordination."

While IEDM was in full swing, there was a timely suggestion that this may be happening, with Iain Thayne s University of Glasgow group announcing that it had received $2.5 million to work with the US-based Semiconductor Research Corporation on a III-V n-channel for next-generation CMOS.

Another company with some involvement is Freescale, for whom Matthias Passlack delivered an invited presentation. Collaborating with Thayne s team, Passlack and colleagues have now made MOSFETs on both GaAs and InP platforms. In his first IEDM visit since 1995, Passlack was clearly struck by the upsurge of interest in III-V CMOS, joking that 12 years ago he was one of just a couple of "nerds" working on it. "Now we have a few more nerds," he grinned at the packed conference room, which by then had become standing room only.

At the moment it is not clear whether the likes of TSMC, Samsung, ST Microelectronics and the other big hitters are prepared to follow the lead and help to solve the various problems. But, if the next few months see more companies launch research programs in this area, and more government-sponsored work at locations such as the Glasgow laboratory, then III-V CMOS could become the real deal.

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