News Article

Europe Launches Flagship III-V CMOS Project

Exploiting an impressive range of knowledge and backing, the DUALLOGIC collaboration likes its chances of being the first to produce dual-channel CMOS.

by Andy Extance
The battle to integrate III-V materials into logic has been joined by a further large research project, armed with €5.8 million ($8.5 million) in European Commission funds.

The three year project, called DUALLOGIC, will attempt to produce the first dual-channel CMOS technology employing III-V compounds for the n-channel and germanium for the p-channel.

DUALLOGIC is a three-year project, which officially commenced at the beginning of 2008. It boasts a total budget of €9.1 million including contributions from its partners.

The project is being led by Athanasios Dimoulas from Demokritos, the Greek national center for scientific research, who previously ran the ET4US III-V logic project (see related stories).

Glasgow University is one of the key sites in the European effort, even though it is already working on a III-V n-channel project for the US-based Semiconductor Research Corporation (SRC).

However, the DUALLOGIC project manager at Glasgow, Asen Asenov, says that the latest project possibly holds greater potential than the SRC effort thanks to the presence of a third experienced semiconductor integration campaigner.

"In Europe we have some advantages," Asenov claimed, "mainly because IMEC s pilot line provides very good material co-integration, which is not available in the SRC project."

IBM, which is also backing the SRC project, will perform work at its Zurich-based research center to assist IMEC at the integration stage.

That effort will help the project onto IMEC s 200 mm wafer co-integration line, using 65 nm node processing. Although the dual-channel approach that DUALLOGIC is taking is targeted to be industrially applied at the 22 nm node, the IMEC line will provide a proof-of-concept.

Adding further to the all-star line-up are NXP and ST Microelectronics, who will model 22 nm node circuits and integrate germanium onto 200 mm silicon-on-insulator wafers, respectively. Aixtron will be developing equipment for epitaxy of III-V materials on germanium.

Although it can t claim to dominate CMOS manufacturing generally, Asenov at least hopes that in integrating III-Vs with silicon Europe can lead the world.

"Europe is leading the III-V MOSFET field," he said, "and we have also good germanium technology."

"Conceptually we are ahead in the game."

• Glasgow University says it received a total of £750,000 ($1.5 million) for its contributions to DUALLOGIC and two further European future-logic projects, NANOSIL and REALITY.

Author
Andy Extance is a reporter at compoundsemiconductor.net

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