IQE's Epiwafers Unite III-Vs And Silicon
Uniting III-Vs and silicon promises to offer the best characteristics of both materials, while enjoying the benefits of large wafer sizes. However, despite more than 20 years of effort, this marriage is still experiencing some teething trouble.
Initially, development focused on GaAs and its lattice-matched and strained ternaries, such as AlGaAs and InGaAs. These materials were promising candidates for RF applications because they could perform some of the functions traditionally associated with silicon CMOS. But this goal was never fulfilled, despite significant efforts from several research groups and major semiconductor manufacturers, such as IBM and Motorola. The poor material quality of the III-V-on-silicon wafers has thwarted progress, alongside the inferior technology for scaling down III-V feature sizes.
The semiconductor industry is now seeing something of a renaissance in the development of III-Vs-on-silicon, which is viewed as the leading candidate for future high-speed digital logic. At IQE s North America manufacturing plant in Bethlehem, PA, we are supporting this effort by providing customized MBE-grown epiwafers for three different projects: a program run by the US Defense Advanced Research Projects Agency (DARPA) called Compound Semiconductor Materials on Silicon (COSMOS); a separate venture led by Intel to build III-V CMOS; and a similar effort led by Peide Ye from Purdue University.
The COSMOS project, which is led by Raytheon and includes contributions from Teledyne Scientific and MIT, involves monolithic integration of clusters of compound semiconductor devices into silicon CMOS chips. These III-Vs equip the silicon wafers with a level of broadband RF performance that is not possible with conventional CMOS.
In Raytheon s case the clusters are made from III-V circuits based on traditional InP double-heterojunction bipolar transistors and HEMTs. These must be compatible with CMOS and III-V fabrication processes on the same wafer.
High-quality III-V epitaxy is carried out in window openings on a substrate compatible with the silicon CMOS, followed by the final fabrication of multilevel integrated silicon CMOS and III-V circuitry.
The effort led by Raytheon is just one of many projects that are investigating a variety of techniques for cluster integration, from pick-and-place die level or wafer-level bonding to direct growth of III-V on CMOS substrates. The key considerations for any approach include the vertical and lateral isolation of the III-V devices from silicon, acceptable levels of power dissipation, compatibility of the epigrowth process with CMOS fabrication, and efficient interconnection schemes between all of the devices.
We also supply epiwafers to the project run by Intel. This effort, which is similar to that being pursued by IBM and Sematech, revolves around the substitution of silicon with III-V devices in the critical circuits of future high-speed digital CMOS logic applications. The building blocks for this type of approach are high mobility modulated doped structures with both n- and p-type channels.
High indium-content InGaAs is a clear focal point for these higher-mobility channels, although some groups are also working with lower-bandgap InAs/Ga(In)Sb alloys. In Intel s case, III-V buffers are used to enable growth of a high-quality InGaAs channel on silicon. Any III-V CMOS transistors that are produced must be compatible with high-k dielectrics for gate isolation and must also employ a structure that is thin enough for device processing with traditional CMOS fabrication techniques.
For all of the projects that we are involved in, integration is only a success if there is no degradation in the performance of the III-V components. After all, if device performance were to drop off this would offset any of the potential benefits that come from the integration of these materials.
However, producing high-quality epiwafers isn t easy, because growth involves a switch from non-polar silicon to a polar compound semiconductor. This transition often leads to antiphase boundaries and stacking faults in the crystal layers.
An additional challenge is the engineering of the lattice parameter from silicon to the particular III-V alloys employed. This must be carried out while efficiently filtering the threading dislocations that result from growth of mismatched crystal structures. These dislocations – which can be formed at the epilayer-substrate interface or during the growth of the buffer – can propagate into the device s active layers and degrade performance and reliability. The growth process must also prevent cracks and additional dislocations in the epiwafer s surface, which can result from significant differences in the thermal expansion coefficient between the host substrate and the active layers. The surface and layer interfaces must also be smooth enough to ensure good transport properties and high-quality device fabrication.
Selecting the substrate
The advent of specially engineered compound substrates has equipped us with a range of CMOS-compatible alternatives to the standard silicon substrate. However, whatever platform is used, it is still essential that the defect density is minimized during initial nucleation of III-V materials. The growth must also restrict the number of misfit and treading dislocations caused by lattice mismatch.
The most straightforward scheme for uniting the materials is direct growth of GaAs on silicon. However, this approach has a major drawback: issues relating to the polar to non-polar switch and the misfit dislocation have to be attacked simultaneously at the interface between the substrate and the epilayers. With alternative forms of substrate, however, it is possible to address one issue at a time.
It s this latter option that we ve adopted for our role in the COSMOS project, where we have employed growth on Soitec s germanium-on-insulator-on-silicon (GeOI/Si) wafers, which are made by proprietary SmartCut technology. This composite s great strength is that it provides separate, mutually acceptable platforms for the creation of III-V devices side-by-side with silicon CMOS.
Growth of III-Vs on germanium, the top surface of this wafer, is already used for the manufacture of solar cells. It s easier to deposit high-quality GaAs on this surface rather than silicon, due to the smaller lattice mismatch between the materials.
The germanium layer in the composite substrate is just 100 nm thick and is perfectly isolated from the silicon substrate by an amorphous SiO2 layer. This allows the wafer to be put through standard CMOS fabrication processes, so long as the III-V devices can be successfully grown and fabricated within masked windows on this wafer, and these areas can be subsequently masked. The CMOS and III-V devices are electrically isolated by the SiO2 layer, but it is relatively simple to connect them.
A commercial production MBE system with 8 inch diameter substrate capability carries out our InP-based growths on GeOI/Si substrates. The 8% shift in lattice constant from silicon to InP is revealed by X-ray diffraction spectra of this epiwafer (figure 1).
Growth of the epistructure begins with a 0.6 µm thick GaAs buffer and a 1.1 µm thick graded metamorphic buffer that adjusts the lattice parameter to that of InP. Linear grading of InAlAs is used for this layer, which features an inverse graded step that helps to compensate for residual strain from plastic relaxation and thermal expansion. Ideally, this metamorphic structure provides a smooth, defect-free surface that is electrically resistive, as these characteristics are wanted for growth of the active layers.
We independently optimized this buffer for InP HBTs and HEMTs. Our epiwafers were cross-hatched, as are those of InAlAs metamorphic structures grown on GaAs. These InP on GeOI/Si structures are suitable for lithography and device processing as their root-mean-square roughness is only 3 nm, according to atomic force microscopy images.
Our epiwafers also have a clean interface between GaAs and germanium, according to cross-sectional transmission electron microscopy images that reveal the scarcity of anti-phase boundaries, dislocation nucleation and propagation (figure 2). Closer examination of the GaAs layer shows that the anti-phase boundaries quickly annihilate. This layer has a dislocation density below the instrument s lower limit for detection, which stands at 1 × 107 cm–2. The active layers of the InP-HEMT (figure 2) are essentially dislocation free and exhibit abrupt, smooth interfaces. More recent plan-view images on HBT structures with our metamorphic buffer show residual dislocation densities as low as 3.5 × 107 cm–2.
We have evaluated our material with Hall transport measurements and built large-area devices that we have compared against the same device stacks grown on InP. The mobility, µ, and carrier concentration, ns, of our InP HEMTs on GeOI/Si are nearly identical to our reference transistors grown on lattice-matched InP (table 1).
Our InP HBTs on GeOI/Si are vertical transport devices, which makes them more sensitive than their HEMT equivalents to threading dislocations in their active layers. These dislocations are expected to degrade current gain and breakdown voltage. However, our HBTs on GeOI/Si wafers deliver a comparable performance to those grown on InP, according to large-area DC device test structures with 100 µm × 100 µm emitter mesas (figure 3). Both devices have nearly identical base sheet resistance, and very close breakdown voltages, ideality factors, Gummel plots and I-V curves. The HBT that s built on GeOI/Si has an inferior current gain, but the difference is less than 10%.
Small-area HBTs with an fT of 170 GHz have been fabricated from these wafers by our collaborators, Teledyne Scientific. Details of these devices will be presented at this year s InP and Related Materials conference, which is held in Paris on May 25–29.
Results from one of our other projects, Intel s effort at developing III-V CMOS, were reported at last year s International Electron Devices Meeting. This program focuses on the fabrication of InGaAs quantum-well field effect transistors (QWFETs) for digital applications (figure 4), which have already been shown to deliver a superior performance to all-silicon n-type MOSFETs. Gain is double that of the silicon MOSFET when both devices run at the same power, and power dissipation is just one-tenth when both transistors operate at the same speed.
The QWFET is fabricated by direct nucleation of GaAs on misoriented, 4° off-cut silicon. Growth of a graded InAlAs layer follows to reach the InP lattice constant. Careful selection of the growth conditions for nucleation is required once again, due to the switch from non-polar to polar material and the large lattice mismatch between GaAs and silicon. An enhancement-mode HEMT structure is grown on this buffer, which features a strained In0.7Ga0.3As quantum-well. The device has a low density of dislocations, because they are generally confined to the buffer, which is just 1.3 µm thick.
The projects that we are involved with are delivering promising results, but there is more to do. For example, our next contribution to the CMOS project will involve the development of HBT growth processes on patterned silicon-based CMOS wafers.
The integration of III-Vs and silicon is clearly an important goal. Success promises to lead to commercial applications in high-speed mixed analogue and digital circuits for military customers as well as in advanced microprocessors and supercomputers, and also military applications. A few years ago the thought of uniting silicon and the III-Vs would have been just a pipe dream, but now the concept is even appearing on several silicon roadmaps.
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