InGaAs Revolutionizes III-V MOSFETs
It s impossible to deny that silicon is an incredibly successful semiconductor because it forms the key ingredient in a microelectronics industry worth more than $500 billion a year. However, this material still has its weaknesses, and its MOSFETs are limited by their relatively slow mobility. III-Vs, such as GaAs, InSb and InAs, are substantially better in this regard, and this advantage has fueled more than 40 years of development of a compound semiconductor MOSFET. These decades of research have produced several minor successes, but any real progress has been held back by the complexities associated with unraveling the physics and chemistry of compound semiconductor surfaces and interfaces.
The story of the III-V MOSFET began in 1965, when the Radio Corporation of America announced that it had built the first GaAs MOSFET. This transistor produced a very low current, so efforts were soon under way to boost this key characteristic. SiO2 was quickly discarded as a good gate dielectric for GaAs and since then the search has been on for low-defect, thermodynamically stable alternatives.
The most significant advances have occurred approximately every 10 years and have focused on GaAs MOSFETs. Initial breakthroughs included the development of pyrolytically deposited silicon dioxide, silicon nitride, silicon oxynitride and aluminum oxide in the 1970s. Sulphur passivation followed in 1987, which improved the device by cutting the GaAs surface recombination velocity, and 1996 saw the introduction of Ga2O3 and Gd2O3 oxides. These films produce good-quality interfaces, but require a multichamber MBE technique that is unsuitable for high-volume manufacturing.
We have now entered the fifth era of advancement for III-V MOSFETs. This has been led by Intel, which is seeking alternative technologies beyond silicon CMOS. These could include germanium, III-Vs, carbon nanotubes and possibly graphene.
Today s efforts on III-V MOSFETs have expanded beyond GaAs and can be subdivided into those based on arsenides, phosphides, nitrides and antimonides. These compounds have a wide range of bandgaps and carrier mobilities, so they are suited to different applications.
The antimonides, a material system that Intel has been working on in collaboration with the UK defense and technology company Qinetiq, is well suited to high-speed, low-power digital applications. High mobilities are the key here and InSb devices can deliver electron mobilities of 77,000 cm2/Vs.
Phosphides are also suitable for logic applications, whereas GaN-based MOSFETs could potentially improve the output power, dynamic swing and reliability for RF power applications. Meanwhile, GaAs-based MOSFETs promise to deliver higher mobilities and higher breakdown voltages than the silicon LDMOSFETs that are currently being employed in wireless base stations.
The lack of progress made with all types of III-V MOSFET stems from their relatively poor interfaces. Silicon is blessed with a high-quality, thermodynamically stable native oxide that produces very little carrier trapping – its mid-bandgap interface-trap density is typically just 1010/cm2-eV. The quality of this interface results from the passivation of 99.999% of the surface s dangling bonds.
This very high degree of passivation must be replicated in the III-Vs if they are to deliver a similar performance to their silicon cousins. However, this is a real challenge for compound semiconductors because their native oxide is far more complicated. In the case of GaAs, it is a leaky and defective mixture of Ga2O3, As2O3 and As2O5. Such a material causes pinning of the Fermi level, which nullifies the device performance by preventing any bending of the surface potential.
Finding a material that perfectly passivates all of the dangling bonds of gallium and arsenic is a real challenge. Decades of effort in industry and academia has focused on this very problem, which has involved attempts to demonstrate a GaAs MOSFET working under inversion operation – the configuration that s suited to digital applications and employed in silicon. However, all of the researchers have had very little to show for their toil and have tended to turn their back on this field after only producing poor-performing transistors. High currents are a key measure of device quality and these versions have only delivered in the nanoamp or microamp range. This lack of success has left a bad legacy – even today young researchers tend to avoid this field after hearing scare stories of years of effort lost to Fermi level pinning.
The interface issue doesn t just plague III-Vs – it is starting to become something of a headache for silicon. That s because the dielectric properties of silicon dioxide are not good enough for CMOS at the 45 nm node, which has forced this community to search for other compounds that could provide a high-k dielectric solution.
Well funded research in this field began in the late 1990s and has had great success. It is now possible to deposit high-k dielectrics on silicon using atomic-layer-deposition (ALD), a technique that involves the growth of a single-atomic layer of one element, followed by purging of the growth chamber and growth of a second single-atomic layer of another element. Purging follows again and the growth is repeated to form a film. This approach is now a manufacturable technology that can be applied to the 45 nm CMOS node and beyond.
Borrowing from silicon technology
At the end of 2001, while working at Bell Labs/Agere Systems in Murray Hill, NJ, I applied ALD to III-V devices. This was carried out in collaboration with my colleague Glen Wilk, in the same building where the transistor was first invented, and involved the growth of MOS structures with high-k dielectrics Al2O3 and HfO2.
We got off to a great start, with a shocking but very pleasing result. Our first GaAs capacitor – which was fabricated to evaluate interface quality – produced channel modulation, even though it was grown without the prior removal of the native oxide. The reasons behind this success are now understood, because ALD has been shown to produce a "self-cleaning" effect, according to researchers at various institutions including IBM, Rutgers, the National Tsinghwa University in Taiwan, the University of Texas in Dallas and the University of Texas in Austin.
The early successes with ALD sparked a dramatic growth of the III-V MOSFET community, which now includes many leading universities and the industrial giants Intel and IBM. However, transistor currents are still languishing in the 1–100 µA range when operated in the inversion-mode configuration that is required for digital applications (this mode of operation involves the generation of a minority carrier current between the source and drain, which is introduced by the field-effect from the gate bias). These currents are hardly any better than those reported 20 or 30 years ago.
However, vast improvements are possible by employing an InGaAs channel, rather than one made from GaAs, according to research by myself and my colleague Yi Xuan. In 2005 we started to work with InGaAs – a ternary alloy that is already being employed for the conduction channel in GaAs PHEMTs and InP HEMTs. The bandgap of this ternary can be reduced from 1.42 eV (no indium content) to 0.36 eV (no gallium content), which improves characteristics such as mobility and saturation velocity.
We have built a range of inversion-mode surface channel InxGa1–xAs MOSFETs with an indium content, x, of 20, 53 and 65%. These transistors, which contain Al2O3, HfO2 and HfAlO dielectrics deposited by ALD, behave in the same way as silicon MOSFETs, but are expected to show a far higher mobility. The version with the least amount of indium produces a current of 1 mA/mm, but this rockets to 0.4 A/mm and more than 1 A/mm for MOSFETs with an indium content of 53 and 65%, respectively. Our In0.65Ga0.35As transistor is the first III-V surface channel MOSFET that is a real field-effect device with an inversion current of more than 1 A/mm. It even exceeds the upper measurement limit for a standard semiconductor parameter analyzer, which is 100 mA for a 100 µm wide device.
The performance of our 0.4 µm gate length Al2O3/In0.65Ga0.35As MOSFET, which has a conduction channel directly underneath the high-k dielectric, is shown in figure 1. The DC current-voltage characteristics show the variations in the inversion current with gate bias. It is suitable for digital applications because it is normally off at zero bias. Turning it on at a positive gate bias provides a drain current of 1.05 A/mm. This drain current is far higher than GaAs PHEMTs and InP HEMTs, and comparable to GaN HEMTs grown on SiC.
Our device s most promising characteristic is its ability to scale down to a submicron gate length. Hopefully this scaling will continue down to the length scales associated with silicon MOSFETs, because this would lead to 10 A/mm or 10 mA/µm III-V MOSFETs at a III-V 45 nm technology node.
Our III-V MOSFET is in its infancy and there is a lot to learn regarding materials, structures and devices. However, we believe that our advances have resulted from an In0.65Ga0.35As channel that has a very high electron mobility and saturation velocity.
We have found that the changes in surface potential for strong inversion are much less for InGaAs channels than those made from GaAs. More importantly, In0.65Ga0.35As has a charge neutrality level that is typically just 0.15 eV less than the conduction band minimum. This prevents the build up of a large number of negative trapped charges at the interface, which can inhibit the introduction of additional inversion carriers by the field effect.
One of our next goals is to cut the mid-bandgap interface-trap density to 109–1010/cm2-eV. Our current ALD-based process can reduce this density to 1011–1012/cm2-eV, which equates to the passivation of 999 dangling bonds out of 1000. But a manufacturable III-V MOSFET technology demands passivation of 99,999 dangling bonds out of 100,000.
Applications in the community
The silicon CMOS community, which is looking for an alternative device technology for high-speed low-power digital applications, is likely to welcome the introduction of III-V MOSFETs. However, they will insist that they can be produced on silicon wafers of at least 300 mm in diameter. But there may well be a time when it is possible to locally grow germanium and InGaAs on silicon. This could form germanium PMOSFETs and InGaAs NMOSFETs, the building blocks for a new generation of CMOS that still employs silicon substrates, but is not held back by this material s low mobility. However, before we get carried away, we must remember that there is still plenty of work to do to make silicon, germanium and the III-Vs happy bedfellows.
There are also some other potential applications for our high-performance InGaAs MOSFETs. This device could serve low-power RF applications that are less demanding on interface quality. These surface channel MOSFETs can deliver a low gate leakage, large dynamic swing and high linearity.
I am optimistic about the future and I hope that the progress of III-Vs in the silicon CMOS community will parallel that of the high-k dielectrics that were introduced in the late 1990s. That technology is now paying dividends for chip manufacturers and hopefully the III-V MOSFET can follow that path over the next few years.
Response to this article from Matthias Passlack
It is well documented that characterization of insulator/semiconductor interfaces on a wider bandgap material, such as GaAs, requires either quasi-static/high-frequency capacitance-voltage (C-V) measurements at very slow sweep rate, low/high frequency C-V data at elevated temperature, or photoluminescence intensity measurements over a range of excitation intensities.
According to my knowledge, data using the above techniques have never been published for ALD Al2O3 on GaAs. Material suitable to investigate the claimed Fermi level unpinning was provided to Ye s group a few years ago but was never returned to us for characterization. The capacitor data and channel modulation published by Ye s group are simply explained by deep depletion effects, a phenomenon unrelated to interface quality and investigated and publicized by another Bell Lab s group years before Ye s ALD work.
The minuscule performance of enhancement-mode MOSFETs employing ALD Al2O3 on GaAs and published photoluminescence data on in situ fabricated Al2O3 films support the fact that the Fermi level is at least weakly pinned at Al2O3 interfaces with properties similar to native GaAs oxide.
The article repeatedly singles out inversion mode devices as being required for digital applications but fails to mention the deficiencies, such as relatively low channel mobility and that another device type exists that meets CMOS requirements as well.
Such devices work either in flatband or accumulation mode, have been demonstrated on GaAs and represent the only III-V MOSFETs fabricated to date with the high electron mobility typical of III-V channels, a device quality interface (Ga2O3/GaAs) and a measured performance as predicted by theoretical models. Comparative Monte Carlo modeling studies have shown that this device type may have even better scaling properties than inversion-mode MOSFETs.
It is general knowledge in the community that the charge neutrality level moves towards the conduction band on an InGaAs surface with increasing indium content. This behavior is unrelated to midgap interface trap density and is only a relocation of the energy position at which the Fermi level preferentially resides.
As such, it is not an improvement but simply a different property of nature. In regard to a device quality interface, the question is entirely different: how easily can the Fermi level depart from the charge neutrality level? In contrast to GaAs with in situ deposited Ga2O3, evidence for the latter has not been forthcoming for InGaAs by Ye s or other groups at this time. Only after this issue has been solved, claims as to CMOS viability can be rightfully made.
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Peide Ye s response to Matthias Passlack
First of all, the comment: "According to my knowledge, data using the above techniques have never been published for ALD Al2O3 on GaAs," is absolutely not true. Low/high frequency C-V measurements at elevated temperatures and under photo-illumination for Al2O3/GaAs were systematically studied and published in reference 1 (see below). Similar studies were also performed on Al2O3/In0.2Ga0.8As/GaAs and published in reference 2.
All of these results have been presented several times at the major material and device conferences as invited or contributed papers. In order to further convince the readers, quasi-static/high frequency C-V measurement is presented at very slow sweep rate, at room temperature and in dark in figure 1. Using the Berglund equation to integrate quasi-static capacitance and obtain the ψs-V relationship, the surface potential (ψs) changes by 1.2 eV, nearly the entire bandgap of GaAs. The Fermi level at ALD Al2O3/GaAs interface is absolutely not pinned.
As emphasized in the feature article and many times in previous publications and conference presentations, the nature of the ALD process itself is also very important. This has now been confirmed as the so-called ALD "self-cleaning" effect by IBM/ASM/Rutgers, the National Tsinghwa University in Taiwan, the University of Texas in Dallas, the University of Texas in Austin, the University of Maryland, Stanford University, IMEC, and many other groups.
The previous photoluminescence experiment on in situ electron-beam-deposited Al2O3 on GaAs is irrelevant to the ALD process, or needs to be revisited. The photoluminescence sample from Freescale is planned and also limited only for organic dielectric studies on GaAs by Northwestern University and Purdue University. It is not for ALD Al2O3 on GaAs. However, the organic dielectric research on GaAs was not continued since neither Northwestern University nor Purdue University secured any research funding on this topic.
The Ga2O3-Gd2O3 work by Bell Labs in 1996 and later by Motorola/Freescale is appreciated by the author. It is always cited as one of the most important references in all of this author s publications in this field and is also noted in the feature article.
Vice versa, the claim that only in situ deposited Ga2O3/GaAs unpins Fermi level or the only "device quality interface" exists on Ga2O3/GaAs is too pessimistic and proven to be incorrect by many publications from different groups in the last few years. For example, the recent publication from the IBM group has demonstrated an inversion-mode GaAs MOSFET with 220 mA/mm drain current on GaAs using ALD Al2O3 as a gate dielectric (reference 3).
In terms of using "flat-band" MOSFET (the more appropriate name is MOS-HEMT) for post-CMOS application beyond the 22 nm node, it is beyond my imagination how feasible it is to integrate the AlGaAs barrier layer (including silicon doping layer), GaAs capping layer, Ga2O3 temperate, GaxGd1–xO insulating layer into one "composite" dielectric to meet the requirement of an effective oxide thickness of around 1 nm.
I strongly believe that our InGaAs work is a contribution to the III-V MOSFET field, not only because we demonstrated record high drain current and transconductance on inversion-mode III-V MOSFET, but also because we are starting to understand how the substrate could play a very important role.
This opens up a new way to "design" the charge neutrality level location or even interface trap distribution in III-V. It is more than "simply a different property of nature" (reference 4). I totally agree that lots of work is needed to further improve high-k/III-V interfaces before III-V MOSFET can become a real commercial technology and hopefully find it applicable for post-CMOS. To realize this goal, it is extremely important for industry and academia to work together and keep the field growing and healthy.
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