News Article

III-Vs And Ge Look To Help CMOS

Scaling down silicon CMOS nodes is getting harder and harder. However, help is on the horizon in the form of III-V and germanium MOSFETs that can improve the performance of n- and p-type channels, say Matthias Passlack, IMEC's Marc Heyns and Iain Thayne from the University of Glasgow.

Cracks are starting to appear in silicon CMOS. Although the International Technology Roadmap for Semiconductors states that MOSFETs with strained silicon channels will be suitable down to the 22 nm node and possibly beyond, projections of device performance indicate otherwise. Studies show a gap will appear between projected and actual performances as node sizes fall to less than 65 nm, and this will only get wider with increased scaling (figure 1).

To make matters worse, history suggests that one of the main sources for transistor improvement is an increase in channel carrier velocity. Recent work by MIT s Ali Khakifirooz reveals that this depends more strongly on low field mobility than was previously believed, which will make it even harder for silicon CMOS to stick to its roadmap.

Fortunately, it should be possible to improve channel mobility significantly by switching to other materials, such as III-Vs and germanium. III-Vs promise to increase electron mobility by 10–30 times, which makes them great candidates for high-speed, low-power n-channel transistors. However, they cannot make good p-channels, which are also needed for CMOS, because their hole mobilities are relatively low. This is where germanium comes in – it has a hole mobility four times that of silicon.

Turning to other materials is not a new idea. In 1986, prototype 16- and 32-bit GaAs RISC processors were developed by Vitesse Electronics Corporation and Texas Instruments. These delivered fast clock speeds of up to 200 MHz, but they were a commercial failure due to high costs and high power consumption. The history of germanium dates back even farther, but this element hasn t been used in mainstream FETs for decades. However, there is good reason to believe that the time has come for III-Vs and germanium to make a lasting impact.

For one thing, the industry is very short of options. It would prefer to steer clear of even more immature technologies, which rules out transistors employing graphene as the channel material and FETs operating via impact ionization or quantum mechanical tunneling. This means that germanium and III-V MOSFETs will be the only real alternatives to silicon in the coming years. Encouragingly, research by Jesús del Alamo s group at MIT, as well as a partnership between Intel and QinetiQ, has delivered some promising results with III-V n-channel HEMTs. These efforts have shown that III-V FETs can be less power hungry and faster than their silicon counterparts at the low supply voltages required for billion-transistor integration.

However, before we get carried away, it s important to realize that there are some massive hurdles to overcome before we can fabricate non-silicon channels in CMOS. These dwarf those that were faced by the industry when it made the recent transition from traditional SiO2 to high-k dielectrics.

Dictated by economics, FETs with non-silicon channels will have to be realized on large-area silicon substrates. This presents a tremendous challenge because it is difficult to unite materials into a near-perfect single-crystal epistructure when they have different thermal expansion coefficients, lattice constants and, in the case of III-Vs, crystal types. Many hours have been thrown at this problem and, although there has been an intensified effort in recent times, potential roadblocks still remain.

Non-silicon transistors are also susceptible to poor off-state performance resulting from the narrower bandgap of the material employed – InGaAs, InAs, InSb or germanium. This increases band-to-band tunneling at the high electric fields that exist at the drain side of the gate of scaled devices, which increases leakage current and cuts the transistor s Ion/Ioff ratio. The density of states available for conduction in high-mobility III-V channels is also less than one-hundredth of that for silicon equivalents.

Some of these changes in material characteristics hinder the performance of inversion-type MOSFETs, the standard workhorse of silicon CMOS. Minority carrier mobilities in surface inversion channels are relatively low. Large surface potentials are needed to produce the surface inversion required for transistor operation, leading to a narrowing of surface quantum wells with large energy quantization, which further reduces the density of states and leads to an increase in the proportion of electrons scattered into satellite valleys. In short, inversion-type MOSFETs may not be the best option for III-Vs.

However, recent work at various groups, including Freescale, the University of Glasgow, UK, and Interuniversity Microelectronics Center (IMEC), Belgium, has shown that it is possible to address some of the problems associated with non-silicon MOSFETs. For example, efforts at Freescale have revealed that progress can be made on the III-V side by turning to flatband- or accumulation-mode MOSFETs, which are promising high-mobility devices.

Flatband MOSFETs
Although the flatband MOSFET is similar to its inversion-mode equivalent – it shares planarity, enhancement-mode terminal characteristics and the ability to be implemented as either a surface or a buried channel device – there are fundamental differences in device operation. The flatband-mode MOSFET, unlike its inversion-mode cousin, is a majority carrier device in the on state and a minority carrier device in the off state. This means that the transistor is able to benefit from the higher majority carrier mobility and increased on-state current, in addition to the potentially lower off-state leakage current. This reduction in the leakage current can result from both deep depletion within the device and minority carrier extraction measures.

All non-silicon MOSFET developers face the challenge of fabricating a satisfactory oxide interface. For decades the only material capable of producing a good enough interface for device operation was a combination of silicon and oxygen. Even today the leading CMOS manufacturers insert a thin SiO2 interfacial layer between silicon and a high-k dielectric. However, promising contenders are emerging for device quality interfaces on germanium, such as ultrathin fully strained epitaxial silicon layers and thermally grown GeO2 with in situ deposited high-k dielectrics. It is also possible to make device-quality oxide–semiconductor interfaces for GaAs-based MOSFETs by depositing Ga2O molecules into the arsenic dimers of a clean GaAs surface. Conventional oxidation – the process used for elemental semiconductors – is not an option because it produces a high density of trap levels within the GaAs bandgap.

Heterogeneous integration is clearly an important challenge but it is not the only criterion for judging the progress of non-silicon FETs. After all, it is not just the device s performance that matters but also its suitability for incorporation into CMOS.

The Intel and MIT groups have built some high-performance n-channel III-V PHEMTs that have a gate length of less than 100 nm, high-channel electron mobilities of 10,000–20,000 cm2/Vs and a superior gate delay and power-delay-product compared with state-of-the-art silicon NMOS transistors. However, their Schottky contact gate electrodes limit scalability and progress in this area will require the addition of oxide layers to address CMOS requirements.

One device that shows promise for fulfilling CMOS requirements is the GaAs-based n-channel MOSFET that we have developed at Freescale and the University of Glasgow. This flatband-mode device, which features a Ga2O/GaAs interface and an In0.3Ga0.7As channel, has been developed for radio-frequency applications and delivers a superior performance to PHEMTs (figure 3). More important is that it has the potential to usurp BiHEMT and BiFET technologies and kick-start a new era of RF front-end integration in applications such as mobile handsets. Success in this market would be driven by the planar MOS configuration, which employs a common epitaxial layer structure allowing single-chip integration of power amplification, RF switching, and digital and analog functions.

These MOSFETs are of limited relevance for CMOS due to their lower mobility compared with higher indium mole fraction InGaAs channel layers. Introducing indium into this layer with a mole fraction of 50% or more requires a switch from a GaAs to an InP substrate. At Freescale we have done this and built a thin-body structure that contains an In0.75Ga0.25As channel by MBE (figure 4). This epiwafer has a mobility of 8000 cm2/Vs, but other MOSFET wafers with similar layer structures have shown electron mobilities of more than 10,000 cm2/Vs – 20 times as great as silicon NMOS.

Our flatband-mode InP MOSFETs deliver an impressive on-state performance – transconductance exceeds 700 µS/µm for a 1 µm gate length. This compares favorably with InGaAs MOSFETs built by both Peide Ye s group from Purdue University and a collaboration between IBM and Princeton. They feature gate oxides deposited by atomic layer deposition, and they have electron mobilities and a transconductance of 1200 cm2/Vs and 230 µS/µm, respectively.

Germanium inversion-mode MOSFETs with a thin epitaxial silicon layer are being developed by IMEC. Such devices can deliver peak hole channel mobilities of more than 350 cm2/Vs on unstrained p-channel devices. Mobility increases to more than 640 cm2/Vs on strained devices – three times as high as the peak value for silicon.

Optimizing implantations and silicon passivation leads to good control of short channel effects and enables devices with a peak transconductance of 800 µS/µm for a 125 nm channel length. At 1.5 V drain voltage this transistor delivers 722 µA/µm – more than double that of a p-channel silicon MOSFET with a 120 nm channel.

If III-V and germanium channel MOSFETs are to provide a viable future beyond silicon CMOS then they will have to scale to diminutive CMOS dimensions. However, it s not just a question of physical miniaturization as these transistors must deliver enhanced electron or hole transport properties. In addition, and in contrast to GaAs MOSFETs, there is still the problem of making a high-quality oxide–semiconductor interface for III-V channel materials with CMOS relevance. This problem plagues all of today s high indium mole fraction channel technologies, and it is evident from the difficulty associated with turning the device off (figure 5).

"Everything can be done in silicon" is a claim that our community contests. And with the scaling of CMOS feature sizes delivering diminishing returns, there is reason to believe that with a collaborative spirit the compounds and germanium can gain a solid foothold. Indeed, it is possible that the saying "everything can be done on silicon" will eventually find universal acceptance. But whatever the outcome for non-silicon MOSFETs for CMOS, one thing is certain: the semiconductor community has some exciting and challenging years ahead.

Further reading
A Khakifirooz et al. IEEE Transactions on Electron Devices 55 (in press).
J R Lineback 1986 Electronics June 9 21.
B C Cole 1986 Electronics September 18 57.
S Datta et al. 2005 IEDM Technical Digest 763.
D H Kim et al. 2007 IEDM Technical Digest 629.
R Metzger 2007 May Compound Semiconductor 16.
M Passlack 2006 IEEE Transactions on Electron Devices 53 2773.
A Delabie et al. 2007 Appl. Phys. Lett. 91 082904.
M Hale et al. 2003 J. Chemical Physics 119 6719.
R J W Hill et al. 2007 IEEE Electron Device Letters 28 1080.
R J W Hill et al. 2008 Electronics Letters 44 498.
Y Yuan et al. 2007 IEDM Technical Digest 637.
G Nicholas et al. 2007 IEEE Electron Device Letters 28 825.
M K Hudait et al. 2007 IEDM Technical Digest 625.

CS International to return to Brussels – bigger and better than ever!

The leading global compound semiconductor conference and exhibition will once again bring together key players from across the value chain for two-days of strategic technical sessions, dynamic talks and unrivalled networking opportunities.

Join us face-to-face between 28th – 29th June 2022

  • View the agenda.
  • 3 for the price of 1. Register your place and gain complementary access to TWO FURTHER industry leading conferences: PIC International and SSI International.
  • Email  or call +44 (0)24 7671 8970 for more details.

*90% of exhibition space has gone - book your booth before it’s too late!


Search the news archive

To close this popup you can press escape or click the close icon.
Register - Step 1

You may choose to subscribe to the Compound Semiconductor Magazine, the Compound Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.

Please subscribe me to:


You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
Live Event