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Swedes Push InAs Nanowires For Transistors

Funds flow into the Lund University team that is making devices by wrapping nanowires in heterostructures that include high-k dielectrics.

The Swedish government is pumping SEK24.5 million ($4 million) into the development of transistors which use the latest in InAs nanowire technology.

Lund University received the grant from the Swedish Foundation for Strategic Research on April 10, with the aim of using the transistors in radio-frequency circuits.

The Lund team originally published research on their 50 nm gate lengthnanowire metal-insulator-semiconductor field-effect transistors (MISFETs) in January and March.

“The key thing that we find in the transistor data is that they can operate at low power, so we can reduce the drive voltage," explained Lars-Erik Wernersson, in whose group the work was performed.

Self assembling from the nanowire up also provides an easier way to make devices with short gate lengths than conventional lithographic techniques, allowing higher frequency operation and other benefits.

“These guys get gate length for free," commented Iain Thayne, who performs research into future III-V transistors and high-k dielectric materials at the University of Glasgow. “We have to work hard to get that."

The Lund group made an 84 percent yield of functional devices from 100 transistors the team reported in their January Electronics Letters paper. Wernersson also points out that the low standard deviation for device threshold voltage suggests good nanowire diameter uniformity, which can be difficult to achieve.

Gold as base metal
So far, the MISFETs have been grown from gold seeds distributed across InAs substrates using chemical beam epitaxy, but Wernersson told compoundsemiconductor.net that MOCVD will also work.

The substrate behaves as the transistor s source and each nanowire is made with an n-doped InAs upper half on top of an undoped lower half. A “wrap-gate" heterostructure surrounds the wires, grown by atomic layer deposition (ALD) of HfO2, and tilted evaporation of polysilicon and chromium onto rotating samples.

HfO2 oxide layers are made to completely surround each nanowire by depositing the high-k material after removing polysilicon from the sides of the nanowires with hydrogen fluoride. An organic polymer layer then insulates the gate, before a TiAu alloy is finally grown to act as the drain and connect the nanowires.

The highest transconductance observed in the MISFETs is 0.52 S/mm at a drain voltage of 0.5 V.

“The 50 nm critical dimension nanowires do have reasonable and encouraging sub-threshold performance," says Iain Thayne, “but the structures seem to still have some way to go to fully exploit the high mobility properties of InAs."

He also points out that in terms of fabrication III-V materials used in nanowires are likely to remain in the shadow of silicon, as Samsung has already produced silicon nanowires using CMOS process flows. However, Thayne considers that investigating the basic device InAs transistor architecture itself remains valuable.

“We live in very interesting times where alternate device architectures need to be explored and this is one such worthy example of that device screening activity," he said.

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