IMEC Makes Crack-free GaN On 8-inch Silicon
A breakthrough in GaN-based microelectronics could be on the cards, after researchers from IMEC and Aixtron produced a crack-free nitride film on a 200 mm substrate for the first time.
The research, demonstrated in Aixtron s application laboratory using a "CRIUS" close-coupled showerhead tool for MOCVD, suggests that it could be possible to manufacture GaN-based power devices on a low-cost silicon substrate.
Although GaN is widely viewed as a tremendous semiconductor material capable of very high efficiency operation, it is yet to make much of an impact in microelectronics because of the high cost of manufacturing the devices.
With native nitride substrates remaining either unavailable or prohibitively expensive, engineers have to make do with SiC, sapphire or silicon, none of which is ideal for the task.
SiC wafers provide a good lattice match with GaN, but are very expensive to produce. On the other hand, sapphire is cheap enough but its lattice mismatch with nitrides means that crystal defects are a huge problem.
Now, the IMEC and Aixtron collaborators have shown that production on large-area silicon could be a viable option. Marianne Germain, who manages IMEC s efficient power program, said: "Bringing GaN devices to a [price] level acceptable for most applications requires a drastic reduction in the cost of this technology."
"And that is only possible by processing on large-diameter silicon wafers. 150 mm, and then 200 mm are the minimum wafer sizes we need to fully leverage today s silicon processing capabilities."
Crucial to the latest breakthrough is the availability of 200 mm (111) crystal orientation silicon substrates, which were custom-made by wafer specialist MEMC Electronic Materials.
Deposition of a standard layer stack began with AlN epitaxy directly onto the silicon, followed by an AlGaN buffer layer, and a micron-thick GaN top layer. Next came a 20 nm AlGaN layer, before the structure was capped with another 2 nm of GaN.
The resulting wafer showed excellent thickness uniformity (see image) and, says IMEC, good crystalline quality as measured by high-resolution X-ray diffraction.
One problem that still remains is the substantial bowing effect that is caused by the large silicon wafer. At the moment, this is in the range of 100 µm, but Germain believes that an optimized buffer layer will reduce the degree of bowing drastically.
• Aixtron s 300 mm CRIUS tool, which can also be configured for 30 x 2-inch and 7 x 4-inch wafer production, is now set to be used in solar cell development, in another III-V-on-silicon research project.
A team at the Fraunhofer Institute for Solar Energy Systems (ISE) in Freiburg, Germany, will use the reactor to make cells on large-area silicon for applications in terrestrial photovoltaics (see related newsfeed entry for more details).