Antimonides Chase Terahertz Target
A key moment in my career occurred at the 1996 Lester Eastman Conference on High Performance Devices. As I sat through a talk on chirp-superlattice graded-collector InP/GaInAs DHBTs, it dawned on me that a GaAsSb base and an InP collector might dramatically ease the realization of InP DHBTs.
According to this new idea, you would inject "ballistic" electrons into an InP collector from a GaAsSb base, thanks to the position of GaAsSb s conduction band relative to InP (figure 1). Eliminating the need for compositional grading at the base-collector junction would simplify epitaxial growth and permit the use of selective etching techniques for chip processing, while doing away with ternary alloys would also boost thermal conductivity and ultimately make the devices more suitable for use in high thermal-dissipation circuits.
The GaAsSb-based design benefits that resulted included simplified fabrication and a better thermal management, and the HBT eventually showed higher breakdown voltages (figure 2). The injection of electrons across an abrupt junction into the InP collector was also expected to give the electrons a velocity kick as they entered the InP collector, thereby increasing their average velocity and ultimately reducing the transistor collector delay time.
Our initial work on GaAsSb DHBTs was done in collaboration with Simon Watkins, a colleague specializing in MOCVD epitaxial growth at Simon Fraser University, British Columbia. With the support of John Sitch from Nortel, we secured a four-year grant totaling $350,000 from the National Sciences and Engineering Research Council of Canada (NSERC), and initially we targeted 160 GHz transistors for potential laser drivers in 40 Gbit/s communication systems.
Before our proposal could be submitted, we were scooped by papers from Bellcore and Rockwell (Bhat et al., McDermott et al.). In both cases, initial results were inferior to state-of-the-art GaInAs-based transistors, and both companies quickly abandoned work on GaAsSb-based devices.
The Bellcore/Rockwell results played on our minds: we were facing some high-risk research. In the end, we decided that we really wanted to attempt the development of antimonide-based DHBTs. Winning funding was a long shot, but we were successful, and work started in earnest in 1997. Back then, very little was known about GaAsSb-InP heterojunctions, so we began by growing this heterostructure and measuring its band alignment (Hu et al.).
Later that year we were approached by Nick Moll, a senior member of the technical staff at Agilent (then Hewlett-Packard) Research Laboratories, who also had an interest in InP/GaAsSb DHBTs. A separate collaboration was then set up with Moll and Agilent to develop the technology.
Our collaborations with Nortel and Agilent were very fruitful and, because neither had InP/GaInAs HBT products, both were receptive to new ideas. The companies initially kept all options open through the simultaneous investigation of GaInAs and GaAsSb DHBTs. Eventually, both opted for the commercial development of GaAsSb DHBTs.
Nortel s efforts were grounded when Bookham acquired its III-V group in the wake of the telecom bubble, but Agilent was successful, and became the first and only organization in the US to commercialize InP/GaAsSb DHBTs. Agilent still doesn t reveal much about its InP/GaAsSb DHBT plans and products, presumably for strategic and competitive reasons, but it is interesting to note that the Santa Rosa, CA, fab where InP/GaAsSb DHBTs are now manufactured is one of the few semiconductor assets retained by the company.
Transitions to industry
In 1998 the characteristics of our first transistor with ballistically injected collector electrons appeared in print (Matine et al.) and two years later we followed it up with the first report of a bipolar transistor with an fT and fmax in excess of 300 GHz (Dvorak et al.). Such performances represented a milestone for any material system, and our measurements were independently verified by Tom MacElwee at Nortel. These NSERC-funded results set a record for bandwidth per invested dollar.
Nortel left the game, but a basic process without passivation and interconnects was transferred to Agilent s Research Laboratories in Palo Alto and adapted for production at the company s Santa Rosa location. Martin Dvorak, my first PhD student at SFU, went on to join Agilent s Santa Rosa facility to develop InP/GaAsSb DHBTs there. By 2004 these devices had become commercial products, also thanks to Moll s tireless advocacy. Moll played a key role in establishing a manufacturable GaAsSb device process meeting Agilent s cost, yield, performance and reliability requirements.
Today, few companies are making money selling commercial InP DHBTs. However, we are pleased to see that, whether researchers are pursuing GaAsSb, GaInAs or SiGe technologies, bipolars or FETs, there is a fair chance that they are characterizing their high-frequency devices using one of Agilent s high-speed instruments with InP/GaAsSb DHBTs inside.
What matters: fT or fmax
Our group continues to develop GaAsSb-based DHBTs, although we relocated to ETH Zürich in 2006. We re continuing to develop faster transistors and one of our goals is a terahertz device. Claims for high speeds can be made in terms of fT or fmax, and it is important to consider these terms and their meanings (see "Understanding fT and fmax").
Once the origins of current and power gain in transistors are understood, particularly that the power gain depends on the termination of input and load impedances, it makes sense to refer to a terahertz transistor as a device with an fT of 1 THz, because such a transistor will feature a sufficiently fast electron transport to maintain a current gain of at least unity at that frequency. Such a terahertz transistor may or may not show power gain at 1 THz, depending on input/output matching impedances and/or on whether the device has been "unilateralized" (i.e. on circuit conditions external to the transistor).
Measuring the speed of transistors with cut-off frequencies exceeding 500 GHz requires care. The fT is determined through extrapolation over wide frequency ranges and calibration subtleties can produce erroneous conclusions. To make matters worse, unilateral power gain does not necessarily roll off at the –20 dB/dec rate that is used in such extrapolations. This means that the implementation of amplifiers or oscillators is the true test for those primarily interested in fmax.
It s also not very simple to relate the transistor figures of merit fT and fmax to digital IC performance. For starters, digital operation is no longer "small-signal", the condition that is assumed for the definitions of these two figures of merit. Furthermore, switching transistors face neither short-circuited nor impedance-matched loads.
Some people in this field follow a rule of thumb that states that digital circuits require fT and fmax values that are three to four times as great as the intended bit rate. Consequently, 40 Gbit/s circuits would need to use transistors with an fT and fmax of at least 160 GHz. However, glaring counter-examples to this rule-of-thumb can be found in the literature, with data rates approaching the fT and fmax cut-off frequencies. Increasingly, workers are finding that the raw fT and fmax cut-off frequencies are weakly correlated to achievable data rates in digital ICs, and efforts are being made to define alternative, more pertinent transistor figures of merit.
Progress was made on this front through detailed numerical simulation by investigating the impact of transistor physical parameters and figures of merit on the maximum achievable data rates in digital circuits (Ruiz-Palmero et al.). These simulations did not rely on device circuit models but rather employed a fully calibrated physical hydrodynamic (HD) simulation of all of the transistors making up the emitter-coupled logic and current-mode logic test circuits. Unlike drift and diffusion models, the electron s energy in high electric fields is accounted for in HD simulations. The Ruiz-Palmero study avoids the approximations that are involved in SPICE-like circuit simulations based on compact models and/or in the development of analytical gate-delay expressions from equivalent circuit models.
These simulations show little correlation between fT, fmax and the minimal gate delay. Instead they suggest that adequately scaled InP/GaAsSb DHBTs with an fT of 1 THz and an fmax of just 600 GHz could deliver data rates of up to 300 Gbit/s. In these simulations, type-I and -II transistors were both optimized to maximize data rates, and fT and fmax cut-off frequencies were merely treated as side products of the optimization procedure.
The important point is that the results dismiss the notion that high-speed digital ICs demand a transistor with an fmax of greater than fT. These simulations showed that whereas both type-I InP/GaInAs DHBTs and type-II InP/GaAsSb DHBTs could be used to implement 200 Gbit/s digital ICs, only the InP/GaAsSb DHBTs could be sufficiently scaled for higher data rates of at least 300 Gbit/s (Ruiz-Palmero et al.), thanks to the favorable breakdown voltages and thermal properties of full InP collectors.
At last December s International Electron Devices Meeting in Washington, DC, we unveiled the results of our new graded-base devices (figure 3). These transistors had a conservatively estimated fT of 600 GHz at room temperature and a breakdown voltage (BVCEO) of 4.2 V, which equates to a fT × BVCEO figure of merit of more than 2.53 THz-V. Cooling to cryogenic temperatures improved all three characteristics. Measurements on a chuck held at 5 K produced an fT of 705 GHz, a 4.4 V breakdown voltage and an increase in the product of fT and BVCEO to more than 3.10 THz-V. In comparison, SiGe HBTs with a 500 GHz fT at cryogenic temperatures feature a much lower fT × BVCEO product of