Trenches Turbocharge Silicon
CMOS engineers dream of exploiting the properties of superior materials in their silicon devices. Semiconductors that pique their interest include III-Vs such as InAs and InSb, which have far higher electron mobilities than silicon, and germanium, a material with faster holes. If InAs and germanium were used for the n- and p-channels of a CMOS device, then it is theoretically possible to cut power consumption by an order of magnitude, without any sacrifice in chip speed.
Such an advance would have a tremendous, widespread impact. Benefits include dramatic increases in the lifetime of portable devices and massive energy savings at server farms.
The potential pay-offs have not gone unnoticed and they continue to inspire major research efforts to develop III-V and germanium devices for CMOS applications. Industry heavyweights IBM, IMEC, Intel and TSMC have all dedicated substantial programs towards this goal, as have many universities. But even the expertise of all of these researchers is yet to surmount the significant technical barriers that are preventing the commercial realization of III-V and germanium CMOS.
The biggest obstacle is also the most basic: how can III-V and germanium materials be united with silicon without any detriment to their high mobilities? This question is the most pertinent, because it is hard to envisage a CMOS industry based on anything other than silicon. Billions of dollars have been invested in developing sophisticated technologies to process silicon wafers, and any switch to another material would be prohibitively expensive.
The ultimate CMOS solution that complies with this restriction involves integrating the optimum materials for electron and hole transport in the channels of the NMOSFET and PMOSFET, respectively (figure 1). However, realizing this dream is very challenging, and today alternative channel devices are nothing more than a laboratory curiosity.
But recent advances in the field of heteroepitaxy – the epitaxial growth of one crystalline material on another – indicate that the problem is not insurmountable. Improvements have been made for several decades, and at AmberWave, Salem, NH, we have recently pioneered a heteroepitaxy breakthrough. We have developed a technology called aspect ratio trapping (ART) that promises to allow the fabrication of the transistor structures that can lead to the realization of germanium and III-V CMOS.
Efforts directed at the heteroepitaxy of germanium and III-Vs with silicon date back to the early 1980s, and the intervening years have witnessed the development of many different techniques to try and unite these semiconductors. On every occasion the focus has been directed at the fundamental problem associated with the transition between two crystals: a large lattice mismatch that creates a high density of atomic dislocations in the epitaxial layers. The variations in lattice constant are between 4 and 8%, and this gives rise to a threading dislocation density in directly grown epilayers of typically 109 cm–2.
These defects hamper device performance. They scatter carriers, reducing their mobility; they trap carriers and shorten their lifetime; and they act as diffusion pipes, which increase the leakage current in the device. If the transistor is to deliver a reasonable performance, the dislocation density must be no more than 106 cm–2, and any manufacturable technology could require far fewer defects than this.
Optimizing direct epitaxial growth on silicon is the most obvious approach to cutting the dislocation density. This method of forming germanium, GaAs and InP layers on silicon has been extensively studied by independent research teams, using MBE and MOCVD deposition technologies. These efforts have produced significant reductions in the threading dislocations caused by lattice mismatch, but the residual dislocation density is still about 108 cm–2. In the early 1990s Eugene Fitzgerald and colleagues at Bell Labs, and Bernie Meyerson and co-workers at IBM, independently explored an approach that tackles these residual dislocations.
By turning to a compositional graded buffer, these researchers could gradually increase the lattice constant during epilayer growth and slash the dislocation density in the top of the epitaxial film by a factor of 104 (figure 2b). These teams had to use a miscible material system to produce intermediate lattice constants between silicon and the desired epitaxial lattice constant. The SixGe1–x system has proved to be convenient for this purpose.
The downside of the graded buffer is its thickness and many types of thinner buffer have been explored. A recent example of this line of enquiry comes from researchers at IHP (Innovations for High Performance Microelectronics) in Frankfurt Oder, Germany (figure 2c). They have shown that thinner buffers are possible by turning to crystalline dielectrics.
Another approach to reducing the residual dislocation density in mismatched epitaxial materials involves epitaxial growth in a confined area, followed by cyclical annealing (figure 2d). This technique, which was pioneered by Lionel Kimmerling’s group at MIT, uses the stress introduced by cyclic annealing to drive dislocations in the mismatched epitaxial film to the edges of the epitaxial area.
Although all of these techniques have enjoyed some success, none can approach the ideal solution depicted in figure 1, p21. The graded buffer, which is 10 μm thick for germanium growth on silicon, is far too thick for CMOS processing, and this ultimately restricts integration to a single material. Thinner buffers, however, have dislocation densities that are too high, while the effectiveness of cyclic annealing is insufficient because some types of dislocation do not move in response to stress and the thermal cycling is too hot for CMOS processes. Put simply, it is not easy to grow low-dislocation III-Vs and germanium on silicon suitable for CMOS.
Aspect ratio trapping
One approach that appears to marry germanium and the III-Vs with silicon successfully, however, is our heterointegration technique, ART. This involves the growth of a mismatched layer on a silicon substrate that contains an additional dielectric layer, which is patterned with high-aspect-ratio holes or trenches. The side walls of the holes in this dielectric trap dislocations originating at the silicon/epitaxy interface and enable the growth of very-low-dislocationdensity epitaxial material at the top of the trenches.
Our ART technique comes very close to delivering the ultimate CMOS device. One of its strengths is the very thin trapping layer, which is 100 times thinner than the graded buffer. This can be realized with 100 nm wide trenches, leading to the fabrication of structures that are compatible with CMOS processing. And thanks to the flexibility of the technique, different materials such as germanium, GaAs and InP can be selectively integrated on different portions of the wafer.
Dislocation trapping in high-aspect-ratio openings was first demonstrated in 2000 by Fitzgerald’s group at MIT. Efforts were led by Thomas Langdo, with collaborators including Anthony Lochtefeld, a co-author of this article, who was a student of MIT professor Dimitri Antoniadis. The key result was the extremely effective defect trapping in high-aspectratio 100 nm wide holes in SiO2, for germanium grown on silicon via ultra-high vacuum CVD.
AmberWave’s long-term research program on ART kicked off in 2005. Several significant breakthroughs followed, which have helped ART to become a realistic option to enable alternative channel CMOS.
Our initial advances involved germanium growth in the narrow trenches of 500 nm thick SiO2 films using an ASM Epsilon reduced-pressure CVD reactor. In work led by Ji-Soo Park, we demonstrated that ART is capable of working in trenches of arbitrary length (figure 4a) as well as it had in holes.
Subsequently, in a project headed by Jie Bai, a former AmberWave engineer who is now at Intel, it was shown that dislocations in films with a high lattice mismatch are preferentially orientated perpendicular to the surface of the epitaxial growth. By choosing conditions favoring steep facet formation in a trench early in the growth, it is possible to produce extremely effective dislocation trapping. The facets guide the dislocations to the dielectric sidewalls.
Our next significant advance was the growth of a variety of key materials, including GaAs and InP, by MOCVD (figure 4b). Jizhong Li and co-workers showed that dislocation trapping may universally apply to materials with a cubic lattice structure, such as the binary materials InAs and InSb, and ternaries such as InGaAs and HgCdTe.
More recently we have shown that the dislocation density can remain at a low level when germanium is grown up and out of the trenches. By combining ART with epitaxial layer overgrowth and chemical mechanical polishing, we have gone on to produce 20 μm wide stripes of low-dislocation-density germanium on silicon (figure 4c). Layout restrictions imposed by the trench geometry are thwarted, making ART applicable to virtually any device geometry used in a CMOS layout.
This sequence of milestones in the heteroepitaxy of semiconductor materials onto silicon has been followed by an advance in CMOS. In partnership with Peide Ye’s group at Purdue, we have produced a GaAs MOSFET on silicon using ART (figure 5).
Device fabrication began with reduced-pressure CVD deposition of germanium, which grew up and out of the trenches to coalesce into a contiguous film. Chemical mechanical polishing planarized this film, before GaAs was deposited by MOCVD. A high-k dielectric was added by atomic layer deposition and then a GaAs MOSFET was created on the planar ART films.
Although these devices are primitive from a scaling perspective – they have a gate length of 10 μm, more than 100 times that of state-of-the-art CMOS – fundamental device results are incredibly encouraging. Electron mobility in these transistors is 503 cm2 V–1 s–1, a value higher than that seen in silicon devices and matching that produced by GaAs devices grown on native substrates.
What’s more, the advantages of ART are not restricted to MOSFETs – they have the potential to deliver improvements in many other electronic and optoelectronic devices. In the past year we have used ART to produce GaAs resonant tunnelling diodes, which are being investigated for post-CMOS logic and memory applications, in partnership with Sean Rommel’s group at RIT. In collaboration with Sarnoff Laboratories we have recently produced GaAs lasers on silicon that will aid the quest for highly integrated photonic circuits, as well as board-toboard and chip-to-chip optical interconnects. Solar cells could also benefit from ART, which has the potential to create multijunction cells on a low-cost silicon platform. In short, ART could transform many types of heterogeneous device.