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IEDM To Highlight Novel Memory Solutions

IEEE release details of upcoming IEDM topics

The IEDM is a conference for the presentation of applied research in microelectronic, nanoelectronic and bioelectronic devices. It will be held in Baltimore this year because of extensive renovations at the usual East Coast venue.  Some 215 papers will be given by researchers from corporations, universities and government labs worldwide.

 


One noteworthy late-news paper describes a record small SRAM memory cell size made with non-conventional lithography. Researchers from the National Nano Device Laboratories (Taiwan) and UC-Berkeley built a functional 0.039µm2 6T SRAM cell using a maskless, photoresist-free, nano-injection lithography technique.  ("6T" is a measure of cell density.)  The cell is just 43-percent the size of the previously reported smallest SRAM cell.  The nano-injection lithography employs a gas-phase chemical reaction - activated with a finely controlled electron beam - to deposit a desired nanometer-scale hard mask pattern for subsequent etching.

 


 The reaction can deposit both dielectric and conductive masking materials.  The lithography process incorporates a full TiN gate and dynamic supply-voltage regulator, and promises to be a low-cost way to perform device and circuit verification for 16-nm technology development. (Paper #17.6, "16nm Functional 0.039mm2 6T-SRAM Cell with Nano Injection Lithography, Nanowire Channel, and Full TiN Gate," Hou-Yu Chen et al, National Nano Device Laboratories (Taiwan) and University of California-Berkeley)

 


 Another significant late-news paper addresses the need for ultra low-power devices.  Penn State, Cornell and IQE Inc. researchers will describe an interband tunneling field effect transistor (TFET) built on InGaAs.  It features on-current of 20µA/µm at 0.75V and a large on-off current ratio of 104, all the more impressive considering the size of the device: its channel length is only 100nm. 

 


The team achieved this performance by fabricating a gate-modulated Zener tunnel junction at the source, to provide for a more abrupt (e.g. more desirable) current turn-on.  In addition, the vertical architecture allowed for high-quality in-situ doped junctions that reduce leakage when the device is off. They built a 6T SRAM memory cell, which demonstrated excellent read/write noise margins down to a 0.3V supply voltage. (Paper #13.7, "Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications," S. Mookerjea et al, Penn State/Cornell/IQE Inc.)

 

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