News Article

IEDM Showcases The Strengths Of III-V Transistors

Highlights from IEDM 2009 include the development of novel, normally-off GaN transistors for power electronics and improved gate dielectrics for III-V transistors targeting logic applications. Richard Stevenson reports.

The 2009 International Electronic Devices Meeting (IEDM) had a similar flavour to its recent predecessors: developments in silicon CMOS technologies dominated the agenda, but there was also a smaller number of papers detailing important breakthroughs in III-V devices. Several of these focused on GaN-based devices for high-power electronics, and a handful described breakthroughs relating to successors to silicon transistors for logic applications.



Panasonic, NEC and HRL Laboratories all reported advances in normally-off transistors that can be used to perform functions such as switching a DC signal to an AC form, or boosting output voltages. Both of these types of manipulations are needed in circuits built for motor drives and for the linking solar panels to the grid.


Researchers from Panasonic claimed to have made the first single chip, GaN-based inverter IC for motor drives. Their device, which converts a DC source into an AC form, has led to the filing of 141 domestic and 90 overseas patent applications.


The inverter features six of the company’s gate injection transistors (GITs) integrated onto a single chip. These transistors are normally-off, which means that they are inherently safer and use a more robust mode of operation that the more common normally-on transistor. The GIT also has a very low switching loss, enabling the construction of an inverter with a conversion loss that is 42 percent less than that of the incumbent technology – a silicon-based insulated gate bipolar transistor.


The epistructure for Panasonic’s inverter is grown by MOCVD on silicon substrates, and normally-off operation is realized through a p-type AlGaN gate above the AlGaN/GaN heterostructure. The authors from Panasonic claim that the transistor delivers an extremely high drain current and a low on-state resistance, thanks to conductivity modulation resulting from hole injection from the p-type gate. Every transistor in the chip has to be fully isolated from the other five. This is realized with an iron ion doping process that is even remains stable at temperatures well above 1000 degrees C.


Device testing reveals a typical off-state breakdown voltage for the GITs of 700 V, thanks to the thick GaN buffer layer. The threshold voltage and off-state leakage current are stable for over 1000 hours, according to biastemperature reliability studies.


The engineers at Panasonic have used these transistors to form inverter ICs. Fast recovery diodes are not used in these circuits. Although they have a recovery time of just 50 ns, they are inferior to Panasonic’s GITs that recover in just 20 ns.


The 2.5 mm by 2.7 mm inverter built from these transistors employs GITs with a 25 nm gate width. This monolithic chip can deliver an operating efficiency of 93 percent, even at low output conditions of 20W out of a 100W motor driving system, and the researchers claim that even higher efficiencies are possible by cutting the on-resistance in a larger chip.


NEC adds neutralization


Like Panasonic, NEC has been developing a new transistor technology. At IEDM it unveiled a GaN power transistor featuring a novel piezo neutralization technology. This addition to the device aids the control and suppression of electrical currents when the power is turned-off, and leads to low-power losses, high-speed switching and high-temperature operation.


The authors of the paper say that conventional HEMTs suffer from a large variation in threshold voltage. This is caused by thickness variations in the AlGaN layer under the gate that is etched down from 20-30 nm to just a few nm to realize normally-off characteristics.


NEC sidesteps this issue with a five-layer design. This is based on a metal-insulator-semiconductor (MIS) FET with a piezo neutralization layer (see figure 1). The MESFET produces normally-off operation, thanks to the switch from

a conventional buffer to one made from AlGaN.


The NEC transistor benefits from the inclusion of a piezo neutralization layer with an identical composition to the buffer. This causes the polarization charges formed between these layers to cancel out, thereby equipping the FET with high threshold voltage uniformity. Realizing similar levels of uniformity in conventional HEMTs is very tough, due to variations in the thickness of an etched layer – in an Al0.15Ga0.85N HEMT, just a one nanometer difference in thickness produces a 113 mV variation in threshold voltage. NEC’s novel transistor also produces a low on-resistance, thanks to the inclusion of an Al0.25Ga0.75N layer. This second electron supply layer has a higher aluminum content than the first one, leading to two-dimensional electron gases in both the channel layer and the piezo neutralization layer. This creates a high sheet carrier concentration of 6 x 1012 cm-2 that gives the MISFET its low on-resistance.


The five-layer structure was grown by MOCVD on 3-inch silicon substrates. Nitrogen ion implantation isolated these devices, and surface passivation was realized by deposition of a SiN film. After a gate footprint was opened in the SiN film, a BCl3 plasma etch created the gate recess. An Al2O3 film provided the dielectric for the MIS gate structure, and a Ni-Au film was employed for the gate electrode in both gate structures. The NEC engineers fabricated Schottky gates across an entire 3-inch wafer, and measured a standard deviation of the threshold voltage of 18 mV using a drain current of 1 mA/mm and a drain voltage of 10V. They say that this variation in threshold voltage is ten times smaller than that for a conventional Al0.15Ga0.85N/GaN HEMT.



Transistors were fabricated with a source-to-gate separation and a gate length of 1μm, and a gate-to-drain distance of 15 μm. At a threshold voltage of +1.5V the MISFET produced normally-off characteristics, a maximum drain current of 240 mA/mm and an on-resistance of 20 Ohm-mm. The three-terminal off-state breakdown voltage was more than 1000 V.

The delegates at IEDM also heard about HRL’s development of GaN HEMTs that were fabricated with a fluorine-based process. They have a breakdown voltage in excess of 1100V, and produce a leakage current of less than 10 μA/mm at voltages below 550V.


The engineering team at HRL took two of the die and formed a boost converter, a device for increasing DC output voltage. This operated at a 200 kHz switching frequency and delivered efficiencies of more than 96 percent for voltages up to 200V, and over 96 percent for voltages up to 360 V. The engineers believe that the efficiency drop at higher voltages is caused by an increase in dynamic resistance and a rise in junction temperature, which could be reduced by improving the heat sink in the GaN package.




Post-CMOS technologies


The handful of papers presented on III-V transistors for logic applications included contributions from SEMATECH, IMEC and Intel. For the last few years IMEC has been working on the development of a germanium channel for p-type conductivity, and an InGaAs channel for n-type conductivity – both types of conductivity are needed to make a suitable successor to CMOS. And at IEDM the Belgium research institute unveiled their latest progress, the development of a common gate stack process involving a sulfur-based treatment and deposition of Al2O3. One of the merits of this approach is that it avoids the need for either interfacial passivation layers or native oxides, such as GeO2, between the channel and dielectric.


Fabrication of the MOSFETs begins by taking germanium and In0.53Ga0.47As substrates, cleaning then, removing their oxides and treating them in ammonium sulfide solution. Atomic layer deposition of 8 nm and 10 nm of Al2O3 on germanium and InGaAs substrates follows at 300 degrees C, before these wafers are annealed at 400 degrees C.


The researchers have studied the interface trap density in both structures. They found a relatively high density ( >1 x 1013 /eVcm2) of acceptor-like traps near the conduction band of germanium, but the density was several hundred times less beside the valence band. With InGaAs the opposite was observed: a relatively high density of donor-like traps on the valence band side, and far fewer defects near the conduction band. These results suggest that it is possible to form a p-channel with a high density of free holes, and an n-channel with good electron conduction and relatively low surface-charge scattering.


Device testing of the germanium and InGaAs MOSFETs revealed drain currents of 600 mA/mm and 200 mA/mm, respectively, at a 2.5V gate bias swing, and maximum transconductances of 340 mS/mm and 95 mS/mm, respectively. On-off ratios for these devices are below 104, partly due to the high off-state leakage current that is believed to stem from the surface leakage paths outside the active area. However, the authors say that this can be addressed through proper device optimization and improvements to the fabrication process.


A US team led by SEMTECH detailed its optimization of a ZrO2 dielectric at IEDM. This oxide is a promising candidate for making a III-V MOSFET, because it has a very high dielectric constant that is four times that of Al2O3. However, the pairing of ZrO2 with InGaAs leads to border traps, interface traps, and interface fixed charges. The US researchers have partially addressed all these issues by inserting very thin (La)AlOX layer between these two materials. Adding this interlayer, which is only about a nanometer thick, cuts border traps and fixed charges by a factor of three, and improves MOSFET performance. Drain current increases by 50 percent, and maximum transconductances by 75 percent.


Intel’s wells


Over the last few years Intel has been working on an alternative to the III-V MOSFET - the quantum well field effect transistor (QWFET). This type of device can be deposited on a silicon substrate, and it delivers an excellent drive current performance at low voltage, but first-generation devices have suffered from a high leakage current at the Schottky gate.


However, the researchers have now addressed this, and at the 2009 meeting they described the characteristics of a QWFET with a gate stack comprising 4 nm of TaSiOX and 2 nm of InP. The new gate slashed leakage current by over three orders of magnitude, and led to the fabrication of 75 nm gate length transistors with a maximum transconductance of 1750 μS/μm, and a drive current of 0.49 mA/μm at a drain-source voltage of 0.5 V.


Although the gate in this device is just 75 nm wide, the other structures are relatively large, and one of the next goals for Intel is to reduce these dimensions while still retaining the ability to move charges in and out of the quantum wells. The researchers from SEMATECH and IMEC face similar challenges, and the developers of nitride electronics at Panasonic, NEC and HRL still have some way to go before their devices can be commercialized. But all these compound semiconductor devices are making progress, and it is a sure bet that even better results will be presented at the next IEDM, which will be held in San Francisco, CA, from 6-8 December 2010.

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