News Article

Processing Of Thin Compound Semiconductor Substrates

In the first follow up to the successful inaugural Compound Semiconductor Industry Awards, Thorsten Matthias, Thomas Uhrmann, Chad Brubaker and Paul Lindner of EV Group discuss their award winning temporary bonding system

Compound semiconductor materials such as GaAs, SiC, LiTaO3 or InP offer distinct electrical advantages, but typically suffer from the low thermal conductivity. The most effective method for heat transfer is wafer thinning. Due to the brittleness of these materials thin compound semiconductor wafers are temporarily bonded to a rigid carrier for thinning and backside processing. The bonded wafers can be processed in standard fabs with standard equipment.

Thermal management of compound semiconductor devices was the primary driver for thin wafers and devices in the past. Recently with the advent of 3D stacked devices and heterogeneous integration the reduced form factor has become an important benefit. For thermal management the wafers are first thinned and then through wafer vias are created. The vias serve both as heat sink and as the electrical grounding for the device [1]. Thinning and subsequent processing of compound semiconductor wafers presents an enormous challenge to the overall production of devices on these materials, as the materials themselves are extremely fragile (much more so than silicon).


Figure 1: Ultra-thin GaAs wafer mounted on a film frame

Processing of front- and backside of a thin wafer can be implemented by two ways. The first approach is that the thin wafer is handled directly. This requires dealing with the problem of thin wafer handling on each individual piece of equipment, which requires specialized wafer cassettes, robot end-effectors, pre-aligners and process modules. This approach has several disadvantages. The required capital expenditures are very high as every piece of equipment has to be upgraded. The bow and warp of thin wafers changes with every single film layer that is added. This means that even if thin wafers of one specific product can be handled directly, it might not be possible to handle thin wafers of another product directly. There is also the risk that changes to the process flow change the stress within the thin wafer in such a way that direct handling is not possible any more.

There are also technical limitations to direct handling of thin wafers as the wafer breakage rate inevitably increases sharply for ultra-thin wafers. The second approach is to temporarily bond the thin wafer to a carrier wafer. The carrier wafer provides mechanical stability to the thin device wafer. Temporarily bonded wafers can be handled and processed like standard bulk wafers. This last point is very important for the cost-of-ownership of thin wafer processing. Adding two process steps, temporary bonding and debonding, enables to run thin wafers in existing fabs with existing equipment.

The generic process flow for thin wafer processing with temporary bonding to a carrier wafer is straight forward. The starting point is a device wafer with complete frontside processing. This device wafer is bonded to a carrier wafer with its frontside in the bond interface. After bonding the first step is back-thinning of the wafer.

Usually back-thinning is a multistep process consisting of mechanical back-grinding and subsequent stress relief etching and polishing. After back-thinning the backside of the device wafer can be processed using standard wafer fab equipment. The carrier wafer gives mechanical support and stability and protects the fragile wafer edge of the thin wafer. When all backside processing is done, the wafer gets debonded, cleaned, and transferred to a film frame or to other output. Temporary bonding and debonding is an enabling technology.

The main benefits of temporary bonding and debonding using a rigid carrier are:

Compatibility with standard fab equipment
The bonded wafer stacks literally mimic a standard wafer. The geometry of the bonded stack can be tailored in such a way that the resulting geometry is in accordance with SEMI wafer standards. This brings the advantage that standard wafer processing equipment can be used without any modification. No downtime at all is required to switch between processing of standard thick wafers and temporarily bonded thin wafers.

Compatibility with existing process lines
With the addition of only two pieces of equipment, the temporary bonder and the debonder, a complete process line or even fab is enabled to process thin wafers.

Compatibility with existing processes
The mechanical and thermal properties of the bonded wafer stack are very similar to a standard thick wafer. This enables the use of existing wafer processing recipes, which have been proven and qualified for standard wafers.

Compatibility with future process flows
The user has the full flexibility to change the processing sequence and the individual process steps for backside processing. After temporary bonding the device wafer is securely protected against mechanical damage. Furthermore, adding process steps or modifying the process flow does not impact the cost of ownership for thin-wafer processing.

Compatibility with product roadmaps
For many devices and products, the roadmaps lead to even thinner wafers in the future. With temporary bonding the entire backside processing becomes independent of the wafer thickness. Reducing the wafer thickness does not require any modifications or adjustments to the processing equipment.

An important consideration is the selection of the rigid carrier. The mechanical, thermal and geometrical properties of the carrier can have significant impact on the wafer processing. The typical choice is a carrier wafer, whose thermal expansion is matched to the device wafer.

Unmatched thermal expansion between device and carrier wafer would result in wafer bow at elevated process temperatures. It is possible to use a carrier wafer out of the same material as the device wafer as this guarantees perfect matching of thermal expansion. In addition a standard wafer as carrier guarantees compatibility in terms of wafer properties e.g. flat position and flat length. This approach is regularly being used for e.g. Si, LiTaO3 or InP wafers. For GaAs wafers frequently sapphire carriers are being used. Many CS wafer fabs employ legacy carrier concepts using oversized carriers. Temporary bonding and debonding is compatible with any kind of carrier independent of material, size and shape.

The temporary adhesive has to fulfil many different requirements. The material has to work with a variety of surface properties and films. The coating method has to be compatible with high wafer topography and bumps. The material has to be rigid at room temperature for backgrinding, resist high temperatures and typical backend chemistries and must not out gas in vacuum. On top of that after all the backside processing has been done, the adhesive has to be debondable and cleanable. This list of requirements explains why extensive material and process qualification is so important. For temporary bonding there are 3 success criteria:

Wafer alignment
It is important that the device wafer is well aligned to the carrier wafer. Obviously any overhanging edge of the thin wafer would result in wafer breakage. For volume manufacturing it is important that the device wafer is accurately centered on the carrier wafer. For all the downstream processes after back-thinning the wafer stack will be registered and pre-aligned based on the perimeter of the wafer stack. Due to the wafer edge bevel the device wafer diameter gets reduced during thinning so that ultimately the perimeter of the carrier wafer becomes the perimeter for the wafer stack. As the SEMI standard for wafer diameter is quite loose it is important to perform a centre-to-centre alignment instead of an alignment with edge pins. Only centre -to- centre alignment with less than 50μm alignment accuracy guarantees high throughput for all downstream processes as the device wafer is immediately centred after pre-alignment.

Void free bond interface
Any entrapped gas bubble can potentially burst the thin wafer during processes at elevated temperatures. Vacuum cavities e.g. topography on the wafer not completely filled by the adhesive, would significantly impact the mechanical stability and the local thermal properties. Therefore it is absolutely necessary to achieve void free bonding. Reflowing adhesives e.g. thermoplastics can fill up all topographical features during the bond process. Dry film laminates can only deal with very limited topography on the wafers. In order to achieve a void free bond interface the wafer bonding system has to provide very good temperature and pressure uniformity.



Figure 2: The fully automated EVG850 Temporary Bonder with dry-film Lamination

Minimal thickness variation
During backgrinding the device wafer will be processed in such a way that the device wafer backside is coplanar to the outer surface of the carrier wafer. The carrier wafer itself has very high co-planarity. However, any thickness non-uniformity of the adhesive layer will result in thickness variations of the thin device wafer. A wedge in the adhesive layer creates a wedge in the thin wafer, whereas convex or concave adhesive layer variations create a convex or concave thin device wafer.

Waxing lyrical
In the past wax was very popular as adhesive. Wax is dispensed at elevated temperatures onto the active device wafer surface or the carrier wafer. On the EVG850TB Temporary Bonding system the temperature of the coating chuck can be adjusted to ensure a uniform layer thickness of the spin coated wax layer across the wafer. The thickness of the spin coated wax layer ranges up to some tens of μm (e.g. 20-50μm).



Figure 3: Schematic process flow of the dry-film lamination module on the EVG®850 fully automated Temporary Bonder for dry-film adhesives





Figure 4: The EVG850DB debonding system integrates debonding of the thin wafer, cleaning and film frame mounting within one system

After coating the substrates get transferred to a bake module in order to remove the solvent prior to bonding. The bond occurs in the bond chamber under vacuum (5e- 2 mbar) and at temperatures up to 210°C. After the bonding step the wafer pair is loaded to a chill module and then transferred to the receive cassette. At elevated temperatures the adhesion of wax decreases drastically allowing debonding of the substrate with very little applied force. The main challenge with wax is the low thermal stability.

Dry film adhesive tapes, especially double-sided thermal release tapes enable higher process temperatures. The EVG850TBL Temporary Bonder is the first production system combining dry film lamination and wafer bonding. The dry-film adhesive tape, supplied to the machine on a reel-to-reel basis, gets punched out according to the requested dimension and is laminated onto the carrier substrate with optical tape-to carrier alignment within +/- 15μm after automatically removing both protective films.

Figure 3 is illustrating the process flow in the dry-film lamination module. Advantages of the punching technology compared to the cutting technologies (laser and blade cutting) are better edge quality for minimum interference with the bonding and back-grinding process, no carrier edge degradation through cutting blades and more flexibility in tape dimension and shapes.

The tape diameter can be chosen to be slightly smaller than the carrier diameter, thus enabling pyramid structured assemblies for minimum wafer edge breaking rates during mechanical back-grinding. The main challenges of dry film adhesive tapes are the limited ability to deal with topography and the moderate total thickness variation of the tapes.

Specialist adhesives
Specially designed spin-on thermoplastic adhesives like the Brewer Science WaferBONDHT 10.10 provide high thermal stability and high chemical resistance. As the material is applied by spin coating the thickness variation of the material is very good even for thick layers up to 100μm. During the bond process the adhesive is reflowing and can fill all topography on the wafer. The EMC-3D consortium [2] has qualified the WaferBOND HT 10.10 adhesive from Brewer Science Inc. for the complete via-last TSV process [3]. Anadigics reported the successful implementation of WaferBOND material and the EVG850 platform in high volume for a 150mm GaAs HBT back-end process [4]

The debonding technology is the cornerstone of thin wafer handling. EVG’s production debonding system EVG850DB integrates debonding of the thin wafer, cleaning and film frame mounting within one system (Figure 4). Alternatively the thin wafers can be loaded into coin stacks or put onto single wafer carriers. For thermoplastic adhesives, a slide-off debond process is used.

Because it’s a thermal release process, slide-off debonding enables both usage of a silicon carrier (as compared to UV debonding which requires glass carriers) as well as non-perforated carriers (compared to solvent debonding). Slide off debonding enables a low-cost carrier – basically a standard silicon wafer. The debonding process itself happens within the adhesive layer, with zero force exerted on the device wafer surface during debonding. After debonding, the residual adhesive layer is cleaned with a single wafer solvent cleaning. The ability to clean the adhesive after debonding is another key specification for a temporary adhesive. It makes the thin wafer handling solution compatible with solder bumps (undercut!) in the interface.

Mechanical debonding would create significant force on the bump with the risk of ripping the bumps off or leaving residue on the wafer. Slide-off debonding has been qualified for wafers with bumps or pillars on the front- as well as backside of the thin wafer [3]

Thin wafer processing is a necessity for many devices in CS wafer manufacturing. Recent advances in material and process technology allow thin wafer processing at high process temperatures and for wafers with high topography like bumps. Ultra-thin wafers with less than 50μm thickness can be processed in each standard fab with the addition of just two process steps, temporary bonding and debonding.

© 2011 Angel Business Communications. Permission required


1. J.S. Kofol et al., “A backside via process for termal resistance improvement demonstrated using GaAs HBT’s", GaAs IC Symposium Technical Digest, 1992, pp267-270


3. J. Charbonnier et al., Integration of a Temporary Carrier in a TSV Process Flow, Proceedings of ECTC 2009, May 26-29, 2009, San Diego, USA

4. Dave Kharas, Nagul Sooriar, „Cycle Time and Cost Reduction Benefits of an Automated Bonder and Debonder System for a High Volume 150 mm GaAs HBT Back-end Process Flow", Proceedings of CS Mantech 2009,

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