News Article

Putting Order Into III-V Surface Oxides

Researchers have produced the first well-defined two-dimensional oxide layers on III-Vs by oxidising InGaAs, InAs, and InSb substrate surfaces.

Oxidised III-V surfaces have a poor amorphous (or polycrystalline) structure and they exhibit defects that are detrimental to device processing. In particular, this problem has hindered the development of III-V channel MOSFETs.

Now a Finnish-Swedish collaboration led by the University of Turku claims to have found, for the first time, that when intentionally oxidised, long-range ordered surface oxide layers are formed at the III-V(100) surface. This provides a model platform to study the oxide properties and a novel template for manufacturing the insulator/III-V interfaces, where avoiding the oxygen reaction is not critical.

What’s more, these findings help toexplain the improvement of device characteristics in a MOSFET incorporating a thermally grown interfacial InAsOx layer as documented in a recent paper [1].

Using a surface-science/engineering approach and ab initio calculations, the team found thatthe crystallisation of the surface oxides arises from an interplay of the initial III-V surface structure, substrate temperature, and oxygen pressure.

The starting GaAs(100), InAs(100), and InSb(100) substrates had a well-orderedc(8×2) surface structure while the InP(100) had the (2×4) structure. The InGaAs(100)c(8×2) surface was obtained by depositing 1-2 monolayers of indium on the pure GaAs and heating the sample up to 500-550 °C. The O2 gas was then introduced into a vacuum chamber, and the O2

pressure set to 3-4×10-6 mbar during the oxidation.


Figure 1 : Schematic showing how the crystalline oxygen-containing surface layer of III-V can be utilised as "part" of the III-V channel MOS


The O2 exposure time varied between 5 and 30 min, and the substrate temperature was 350-520 °C depending on the material (the lowest temperature for InAs and InSb and the highest temperature for InGaAs). These conditions produced smooth topography with two-dimensional islands for the crystalline oxidised surfaces as deduced by low-energy electron diffraction (LEED), scanning tunnelling microscopy (STM), and photoemission. The produced oxide layers were InAs(100)c(4×2)-O, InAs(100)(3×1)-O, InP(100)(2×3)-O, InGaAs(100)(4×3)-O, InGaAs(100)c(4×2)-O, InSb(100)(1×2)-O, and InSb(100)(3×1)-O.


Figure 2 . (A) STM image of the oxidised InAs(100) surface, which shows two crystalline oxide phases with a smooth 2-dimensional nature.

(B) and (C) The corresponding LEED patterns with sharp intensity spots which reveal good crystal quality on a large scale.

The next step for the team is to study the performance of III-V channel MOSFETs with the ordered oxide interface between the III-V material and high-κ (e.g., Al2O3) gate dielectric stack.

Further details of this work are published in the paper:

[1] “Oxidized In-containing III-V(100) surfaces: Formation of crystalline oxide films and semiconductor-oxide interfaces" by M. P. J. Punkkinen, P. Laukkanen, J. Lång, M. Kuzmin, M. Tuominen, V. Tuominen, J. Dahl, M. Pessa, M. Guina, K. Kokko, J. Sadowski, B. Johansson, I. J. Väyrynen, and L. Vitos, Physical Review B, 83, p.195329 (2011). DOI: 10.1103/PhysRevB.83.195329


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