News Article

Plasma Etching For HBLEDs

The goal of every HBLED manufacturer is more light for less money. With strong competition and numerous technology hurdles it is vital that all manufacturing steps are pushed. Mark Dineen, Product Manager (HBLED) at Oxford Instruments Plasma Technology discusses how optimised plasma etching offers several ways to improve device output and reduce costs providing a double windfall.

I have never thought of myself as a veteran, but with over 15 years working on HBLEDs I guess that makes me one. When I first started out, plasma etching was used as a tool to etch down through the p-type layer into the n-type in order to make a contact. Since then we have seen several new applications that mean plasma etching is even more important.

Patterned Sapphire Substrates

Sapphire, at the moment, is still the substrate of choice for growing HBLED structures. However, there are two problems with growing on Sapphire: it is not a perfect lattice match and light extraction is reduced by having two parallel reflecting surfaces. In order to improve both these issues from 2005 onwards companies have been  etching patterns into the sapphire prior to growth. This can give a >98% improvement on light extraction from the finished device.

Sapphire is a very stable material, with a melting point of 2054°C that consequently makes it difficult to plasma etch. However Photoresist (PR) which is used to achieve the very specific pattern definition has an upper temperature limit before it degrades, typically 150oC.

PR is the mask of choice for this process as the ultimate ‘dome’ shape is reliant on all the mask being removed on completion, and the shape is closely linked to the relative etch rates of the sapphire and mask. PR is also preferred as it simplifies the manufacturing flow and reduces the overall Cost per Lumen. In order to etch the material, combinations of Cl2, BCl3 and Ar are commonly used with higher etch rates achieved at higher plasma source powers. However this increases  the heat load on the sample therefore, to use PR as a mask and maintain a high etch rate, it is necessary to actively cool the wafer sample.

Figure 1: Typical dome PSS feature

Figure 2: Shallow GaN etch for device contact PR remains on the sample

The silicon industry is accustomed to clamping single wafers to a temperature-controlled table, and introducing a heat transfer medium, normally helium, between the table and the wafer. ‘Helium backside cooling’ has become the standard method for single wafer temperature control. HBLED manufacturing currently uses batches of smaller substrates, passed into the etch tool on a carrier plate. For Patterned Sapphire Substrate (PSS) etching, HBLED devices are still mostly manufactured on 2" or 4" wafers, therefore to significantly reduce costs it is desirable to process as many wafers in one run as possible.

Etching large numbers of wafers with a PR mask requires good temperature control of each wafer, and this requires an understanding of how to transfer the heat from the plasma away from the samples to the cooled electrode. Helium backside cooling is the key, and understanding how to enable this for every wafer ensures success. Batch sizes for this technique are up to 20 x 2" with etch rates between 50nm/min and 100nm/min depending on the PR mask and PSS shape requirements.

GaN Etching

The chemical stability and high bond strength, it’s melting point, (25000C) and bond energy (8.9eV/atom), associated with GaN also make it highly resistant to wet etching in either acid or alkali based etchants. To date, the lack of a suitable wet etch for processing has resulted in much interest in developing dry etch processes suitable for HBLED production, with the same necessity to etch large numbers of wafers in a single batch. Plasma etch batch sizes have increased from 4 x 2" wafers in the late nineties up to 55 x 2" or 3 x 8" today, the question now is how big can the batch size go before it becomes unattractive. This is mitigated as the wafer sizes migrate upwards from 2" to 4" and then 6". The main areas of GaN etching are:

Shallow contact etch

When etching down to a contact layer it is vital that minimal plasma damage is caused to the semiconductor otherwise an increase in contact resistance can occur. Careful optimisation of the etch process is required to maximise throughput while maintaining device performance. Smooth surfaces typically indicate a high quality etch as shown in Figure 2.

Unoptimised etch processing can lead to threading dislocations in the GaN etching preferentially leading to a pitted surface and increase in contact resistance. Again PR is the mask of choice for this step as it is the most simple process regime. The use of PR leads to a reduction in powers used due to the temperature limitations with typical batch etch rates upto 150nm/min reported.

Deep isolation etch

Etch rate is key to this process as depths of up to 7μm can be required. The function of this step is to etch down the underlying sapphire substrate in between the active devices. As sapphire is electrically nonconducting this isolates the devices before physical separation. The key challenges with this etch step are heat removal if a PR mask is used, as high etch rates are achieved with high plasma densities. This translates as a clamping issue for single wafers and is typically approached using an electrostatic clamp. A dielectric hard mask can be used and this opens the possibility of high etch rate batch processing where uniformity across the batch dictates the yield.

Figure 3: Deep, high aspect ratio GaN etch SEM image from Philip Shields, University of Bath

Photonic crystal patterning

By patterning the light emitting surface of the HBLED with a quasicrystalline array known as a photonic crystal it is possible to improve light extraction. An extreme demonstration of this is shown in Figure 3 where a 600nm feature has been etched 4μm deep giving a >6:1 high aspect ratio structure. Here the challenges are maintaining the vertical profile in the etch feature in order to ensure the optical performance of the photonic crystal.


In order to achieve the high etch rates and low damage requirements the industry has developed several high density plasma sources: Inductively Couple Plasma (ICP);Transformer Coupled Plasma (TCP); High Density Plasma (HDP) . All technologies offer a driven table on which the sample sits and a separate plasma source which enables high plasma densities without an increase in the DC Bias seen by the sample. DC Bias has been shown to increase plasma damage to sensitive surfaces so this is an essential system characteristic. The PlasmaPro NGP1000 etch system, designed for GaN, AlGaInP and Sapphire etch, offers batch sizes up to 55 x 2", 13 x 4", 5 x 6" or 3 x 8", yielding market leading volumes of wafers/month. The HDP Etch plasma source achieves comparable plasma densities to ICP sources, maintaining the benefits of high etch rates and low damage. Other key technologies required for etching batches are: a knowledge and control of plasma uniformity over large areas and the capability to control the sample temperature of multiple wafers under aggressive plasma conditions.

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