III-Vs shine at IEDM 2011

For many decades, advances in silicon have dominated discussions at the International Electron Devices Meeting (IEDM). And that’s still the case today, but in recent times the number of papers reporting breakthroughs in III-V devices has swelled significantly, and it hit an all time high at the 2011 meeting. Compound semiconductor highlights included breakthroughs in III-V logic: The world’s first III-V threedimensional MOSFET made with a ‘top-down’ approach; designs for quantum-well FETs that promise to reduce IC power consumption; and studies showing that MOCVD can be the equal of MBE, when forming III-V-on-silicon transistors. Meanwhile, developments in GaN included the insertion of trenches around the drain to slash leakage currents and the addition of barrier layers to boost diode performance. Claims for the fabrication of the first III-V MOSFET produced with a top-down, foundry-compatible approach came from collaboration between researchers at Purdue and Harvard. The architecture of their InGaAs transistor mirrors that of 22 nm-node silicon MOSFETs that will roll off Intel’s production line this year. The similarity of these two transistors makes the InGaAs MOSFET a strong contender for IC manufacture beyond the 14 nm node. The road map for CMOS predicts that alternatives to silicon will be needed at these very small length scales, and III-Vs are widely tipped to take over. The Purdue-Harvard team is by no means the first to make a three-dimensional III-V transistor: Many other research groups have already achieved that feat, but in every case they have formed nanowire structures with a ‘bottom-up’ approach. “Industry has interest in that work, but not strong interest,” explains Peide Ye, leader of III-V MOSFET research at Purdue University. He points out that bottom-up techniques tend to produce wires that have a random arrangement. “It is difficult to put these transistors where you want, and connect them together to form a circuit.” According to Ye, the silicon industry is far more interested in developments involving top-down approaches. That includes the lithography, dry/wet etching and atomic layer deposition (ALD) processes that he and his co-workers have used to fabricate their MOSFET. Three-dimensional transistors benefit from wrapping of the dielectric around the channel to minimize so-called ‘short-channel effects’. In general, these are exacerbated as the transistor’s feature sizes are scaled down, because miniaturization must include a thinning of the dielectric used for making the gate. When the silicon industry reached the 45 nm node it departed from the traditional silicon dioxide gate, using hafnium dioxide instead to temper short-channel effects. At the 22 nm node these effects are even more severe, so chipmakers are turning to three-dimensional transistors to address this issue. These three-dimensional devices enshroud the channel with a dielectric to control current flow. “It’s the same story happening with III-Vs, because the device physics is, in principle, the same,” says Ye. His student, Jiangjiang Gu, took two years to figure out how to make a gate-all-around III-V MOSFET. He focused on finding a simple approach to making this device that would employ processes suitable for use in a silicon foundry. Device fabrication begins with MBE growth of a 30 nmthick InGaAs layer on p-doped InP. Implanting silicon ions creates source and drain regions, and a lithographic process forms nanowire InGaAs channels (see Figure 1). Anisotropic wet etching with hydrochloric acid removes InP, including that beneath the InGaAs channel. This is only successful when the channel is aligned along the [010] direction, an orientation that produces undercut etching. ALD, which is a ‘super-conformal’ process, wraps the channel in a 10 nm-thick coating of Al2O3 and then surrounds it with a WN gate. A second lithographic step selectively removes part of the WN layer, allowing contacts to be made to the source and drain regions. The MOSFETs that result have been produced with either one, four, nine or 19 InGaAs nanowire channels (see Figure 2). Using multiple wires allows the researchers to not only study their uniformity, but also increase total current delivery. High values for transconductance and drain current showcase the promise of these devices for forming high-speed logic circuits. Devices with a 50 nm gate length have a transconductance of 710 μS/μm, revealing that scaling to small dimensions is not detrimental to transistor performance (see Figure 3). “With our planar devices, after 150 nm you are out of control,” says Ye. Drain current, which has been normalized by the perimeter of the wire to allow fair comparison with results for planar structures, peaks at 1.17 mA/mm for a ‘hero’ device. “That’s a very high current – higher than the III-V bottom-up work.” Typical values for sub-threshold swing and draininduced barrier lowering for a device with a 50 nm gate length are 150 mV/dec and 210 mV/V, respectively. These values are too high, and Ye admits that progress is needed: “The interface is difficult and there is still a lot of engineering work to be done. The sub-threshold slope needs to come down to 65-70.” Reducing the power Another advantage of III-Vs over silicon is their greater potential to reduce the power density in logic circuits. III-Vs promise to work at lower operating voltages, which must be introduced as feature sizes are scaled to prevent a dramatic increase in the power density within the chip. Lu Liu, a graduate student in Suman Datta’s group at The Pennsylvania State University, points out that the obvious applications for low power chips are in battery-powered electronics goods, such as lap-tops, tablets, cell-phones and cameras. However, they can also prevent chip overheating that can lead to premature device failure. Although bolting powerful cooling fans onto CPUs and graphics cards can address this, it’s a workaround that leads to an increase in energy consumption. A far more attractive option is to build circuits from devices requiring considerably lower operating voltages, such as less than 0.5 V. Such devices require higher ‘on-currents’ and a higher ratio between the ‘on’ and ‘off’ currents. This is possible by replacing silicon with materials with higher mobilities: InGaAs for NMOS and germanium for PMOS. To suppress short-channel effects, multi-gate structures are needed, such as the one used by Purdue and Harvard. In Datta’s group, efforts in this direction have led to the development of classical and non-classical Multi-gate Quantum well FETs (MuQFETs) employing a 14 nm-thick In0.7Ga0.3As well (see Figure 4). “We consider the classical MuQFET to be a good candidate for sub-14 nm CMOS and beyond,” says Liu, who explains that the non-classical variant promises to play a role at even more extreme length scales, when the number of electrons passing through the transistor starts to approach unity. “Non-classical MuQFETs in Coulomb oscillation mode are used to realize few and ultimately single electron computing with quantum dots.” Liu and his co-workers have built classical MuQFETs with a 40 nm fin width and non-classical variants with split gates separated by 80 nm. The former can deliver a drive current in excess of 100 μA/μm at a drain source voltage of 0.5 V, and the latter can operate in coulomb blockade mode at 4.2 K (see Figure 5). With device scaling, operation in coulomb blockade mode should be possible at room temperature. The Pennsylvania researchers have also put forward a hybrid logic architecture for sub-250 mV operation, using the pairing of classical and non-classical MuQFETs. “Current complementary logic is not suitable,” explains Liu, “because of the lower current drivability and the low ratio of ‘on-current’ to ‘off-current’ in coulomb blockade mode.” So he and his co-workers used binary decision diagram logic to build logic circuits and harnessed negative differential resistance (NDR) to build static memory systems. Using device models that are well calibrated to these experimental efforts, the team found a 50 percent reduction in minimum energy for logic compared to silicon CMOS. When they used this silicon benchmark for memory, they discovered a 75-fold reduction in dynamic power. MOCVD verses MBE If III-V devices are to be used in ICs beyond the 14 nm node, they will have to be formed on large silicon substrates that can be processed in today’s foundries. However, it is challenging to form high-quality III-V layers on silicon, due to a significant difference in lattice mismatch and a fundamental difference in polarity between the substrate and epilayers. To address this several research teams have learnt how to grow III-V buffer layers on either blanket or patterned silicon wafers. These efforts have been performed primarily by MBE, which offers excellent process control. However, this deposition technique is line-ofsight and non-selective, characteristics that pose challenges for process integration and conformal growth on non-polar, three-dimensional devices. MOCVD is a more promising growth technology for making III-V transistors on silicon, thanks to its strengths of selective area growth and deposition on threedimensional structures. There have been very few efforts in this direction, but at IEDM 2011 a partnership between Intel and IQE claimed to report the first direct comparison between III-V-on-silicon transistors grown by these two rival deposition techniques. Their conclusions: The material quality of the epilayers deposited by MOCVD is comparable to the best films grown by MBE, and the Hall mobility in the channel of the MOCVD-grown III-V-on-silicon transistor at roomtemperature is as good as that of the ‘gold-standard’ – an MBE-grown, III-V transistor formed on InP. Researchers from Intel and IQE began by comparing the performance of InP films deposited on native substrates by MBE and MOCVD. Multi-frequency capacitance-voltage curves using TiN metal gates and TaSiOx dielectrics deposited by atomic layer deposition revealed that MBE and MOCVD can form InP layers with a low mid-gap density of interface states. The team’s next step was to produce In0.7Ga0.3As QW FETs with a high-k dielectric on InP. Again, MOCVD-grown devices were the equal of those made by MBE: Both transistors delivered similar values for sub-threshold swing and produced comparable plots of ‘on-current’ as a function of ‘off-current’. To compare the two deposition techniques for growth of III-V QW FETs on silicon, the researchers selected 75 mm (100) silicon substrates with a 4° off-cut. According to them, they employed the thinnest buffer ever reported: 0.5 μm of GaAs, followed by a 0.7 μm-thick graded layer of InxAl1-xAs and a 0.1 μm-thick In0.53Ga0.47As bottom barrier. The graded ternary features an overshoot of indium concentration to x=0.7, before the composition is brought back to end at x=0.52. Doing this ensures full relaxation in the buffer and means that the bottom barrier is lattice-matched to a 50 nm-thick, In0.53Ga0.47As QW. Atomic force microscopy (AFM) reveals that the GaAs buffer grown by MOCVD is slightly smoother than its MBE-grown cousin. Its material quality is also better, according to X-ray diffraction. And scrutinizing the interface of silicon and GaAs with cross-sectional TEM reveals yet another advantage of MOCVD: Defects are confined at the interface, rather than spreading through the layer. These characterization techniques have also been used to assess the quality of full epitaxial structures. AFM measurements reveal that the MBE-grown sample is slightly smoother than its MOCVD-based rival, and X-ray diffraction measurements indicate that the material quality of the In0.53Ga0.47As bottom barrier and quantum well are very similar in both samples. Inspection with the TEM indicates a complete lack of defects in the samples grown on InP, and a defect density of 2 x 109 cm-2 in both silicon-based samples, which had defects typically 50 nm by 100 nm in size. Hall measurements reveal very promising values for the carrier mobilities of the MBE-grown III-V FETs on silicon. At 300 K, mobility was typically 8000 cm2 V-1s-1, and at 77 K it exceeds 22,000 cm2 V-1s-1. GaN FETs with thinner buffers An entirely different class of III-V-on-silicon transistors were discussed in a paper by Puneet Srivastava from imec: GaN double-heterostructure FETs featuring a Silicon Trench Around the Drain (STAD) contact. The merit of this novel device is the combination of a 2 kV breakdown voltage and good performance at elevated temperature, despite the use of a relatively thin buffer. With conventional GaN-on-silicon HEMTs, the high breakdown voltage stems from a thick buffer layer – typically 7 μm to realise a 2 kV blocking voltage. If the buffer is much thinner than this, the transistor prematurely fails through interfacial conduction across the AlGaN-silicon interface. Thick buffer layers prevent this but present their own problems, such as strain in the epiwafers that can lead to bowing of the wafer and even crack formation. Previously, imec’s researchers had managed to realise high breakdown voltages with buffers just 2 μm-thick by removing a small region of the silicon substrate between the source and drain contacts. “With this technique, we achieved a high breakdown voltage of over 2 kV,” says Srivastava. “But the devices suffered from enhanced self-heating, because there is no silicon substrate under the gate region [where the heat is generated]. With the STAD approach, the silicon substrate is still under the gate electrode, which has improved thermal performance.” These novel FETs were formed on silicon (111) substrates, because this orientation has a smaller lattice mismatch with AlN than silicon (100). After the epitaxial stack is formed, which features a 3 nm-thick Al0.45Ga0.55N barrier, a 150 nm-thick GaN channel and a 2 μm-thick Al0.18Ga0.82N buffer, the substrate is thinned to 125 μm and trenches are formed around the drain contact with reactive ion etching. To assess the performance of these transistors, the team also produced control devices without a STAD. The breakdown voltage of these devices saturated at 650 V, while the breakdown voltage of the STAD FETs increased with gate-drain distance, exceeding 2 kV for a separation of 20 μm. The transfer characteristics (IDS-VGS) revealed no change in threshold voltage with the introduction of a trench around the drain contact, indicating no deterioration to the two-dimensional electron gas (2DEG) channel. High-temperature performance of the STAD FETs was assessed by measuring the buffer leakage at 100 °C. The team found that this leakage is several orders of magnitude lower than that of the control at 500 V (see Figure 6). Barriers supress leakage A novel GaN architecture has also been developed at Panasonic to deliver low reverse-leakage current, fast recovery times, and a breakdown voltage of 600 V. This diode could be used in power supply circuits, including those fitted to hybrid electric vehicles. In these types of applications, silicon incumbents will compete with SiC and GaN variants in the power switching market. One of the key differences between the two wide bandgap diodes is that GaN has a lateral configuration, while the configuration in the SiC device is vertical. A lateral configuration is superior, according to the Panasonic team, because it has an inherently lower capacitance. “We believe the area of the top electrodes is the dominant origin of capacitance,” says Panasonic’s Tetsuzo Ueda. “By minimizing the area of the top two electrodes, we can reduce the total capacitance with the lateral configuration. We are attaching the electrodes directly to the 2DEG, so we believe we can reduce the area sufficiently.” Panasonic’s novel diode features triple junctions of AlGaN and GaN on a silicon substrate (see Figure 7). The undoped multi-junctions behave as an insulator when the device is under reverse bias, thanks to balancing of the fixed polarization-induced charges at the top and bottom surfaces. This structure, which Panasonic refers to as the ‘Natural Super Junction’, does not require precise control of the doping, and a low operating voltage and contact resistance is possible by applying Ni/Au anode and Ti/Al cathode contacts to the sidewalls of the junctions. This particular structure suffers from a high leakage current, which prevents high operating voltages. But the engineers at Panasonic have recently developed a way to combat that by adding a p-type GaN blocking layer. Simulations show that with this addition the depletion resulting from the p-GaN layer increases the tunnelling distance, thereby supressing the tunnelling currents and the reverse leakage current. The paper presented by Panasonic researchers at the IEDM meeting in Washington detailed devices with this architecture, which were formed using MOCVD. These devices were compared with commercial SiC diodes. This effort determined that the GaN multi-junction diode has a significantly lower capacitance than its SiC rival, produces a blocking voltage up to 600 V and delivers 18 A at 1.5 V. Boost converter circuits have been built with Panasonic’s diode and a GaN-based, normally off GIT, which has an on-state resistance of 100 mΩ and a breakdown voltage of 600 V. Operating at 100 kHz, the efficiency of this convertor exceeds 98 percent, outperforming the combination of SiC Schottky barrier diode and silicon free-wheeling diode that can drive the GaN-based GIT. Panasonic is starting to try and exploit the commercial promise of this diode, which outperforms its SiC rival in terms of circuit-level efficiency and enables a reduction in component count. This novel GaN device detailed at IEDM by Panasonic, plus that described by imec and the advances in III-V transistors reported by many groups, highlights the promise of the compounds to exceed what is possible with silicon. And at IEDM 2012, it’s a sure bet that they’ll be many more announcements echoing this theme.