Uniting GaN and silicon
Researchers from MIT have unveiled a new bonding technology for uniting GaN HEMTs and silicon MOSFETs on 4-inch silicon substrates using foundry compatible processes. The team, led by MIT’s Tomas Palacios from the Department of Electrical Engineering and Computer Science, have used a thin layer of SiO2 to bond a siliconon- insulator (SOI) wafer, which was capped with silicon, to a AlGaN/GaN-onsilicon epiwafer made by US firm Nitronex.
This work will help to support efforts to combine high-quality transistors made from silicon with those built from nitrides, and ultimately pave the way to the fabrication of a range of novel circuits: Power distribution schemes for silicon microsystems; digital-to-analogue converters combining exceptional efficiency with high power; and a range of new optoelectronic devices on a silicon platform, which could potentially cover a wide spectral range.
Palacios says that it is possible to scale the SiO2 bonding process to larger wafers, which are more attractive from a commercial perspective: “Since we submitted the paper, we have been able to demonstrate 6-inch hybrid wafers in collaboration with [MIT’s] Lincoln Laboratory.” The team is targeting 8-inch wafers by the end of the year. “It is a very interesting diameter,” says Palacios, “because there are many silicon fabs with a good silicon technology that can accept 8-inch wafers.”
The most widely used approach for uniting nitrides and silicon is hetero-epitaxy. But this requires thick buffer layers and straincompensation techniques to address the significant lattice and thermal mismatches between the two types of material. The substantial thickness of this buffer – typically 1.5 μm or more – prevents the use of state-of-the-art lithography in the bottom silicon layer, due to a limited depth of focus.
Wafer bonding with various materials can overcome this issue. Palacois’ group has previously used a hydrogen silsequioxane interlayer for bonding, but particles and contamination in this film hamper scaling of the process. Switching the bonding layer to SiO2 makes a lot of sense. “Silicon dioxide is used in silicon-on-insulator technology all the time,” explains Palacois. “It is a material that bonds very well to itself as long as it is atomically smooth.”
To fabricate circuits based on silicon and nitride transistors, the researchers clean a Nitronex 4-inch epiwafer and coat its AlGaN surface with a 1 μm-thick film of SiO2 using CVD. Heating to 950 °C degasses this wafer, and chemical mechanical polishing creates a smooth top surface.
Organic cleaning prepares the top surfaces of the nitride and silicon-on-SOI wafers, which are bonded by contacting the two wafers under vacuum so that they fuse together. Annealing at 900 °C strengthens this bond, before wet etching and chemical mechanical polishing remove the two top layers: That of the silicon substrate and its oxide.
Standard silicon process technology forms MOSFETs from this hybrid wafer. GaN devices are then added following selective removal of the silicon (100) active layer. This involves annealing the wafer to 870 °C, a step that does not impact the dopant diffusion profile in the silicon devices, according to modelling with the Synopsys’ TSUPREM4 software.
Uniting silicon and nitride transistors by these processes does not degrade their performance, according to the team. Their silicon pMOSFETs, which have a 3 μm gate length, produce a peak drain current of 42.8 mA/mm at a gate-source voltage of -3 V.
Meanwhile, the HEMTs that have a 3 μm gate length and a 1.5 μm gate-source distance deliver a drain current of 420 mA/mm at a gate-source voltage of 1V, and have a gate leakage current below 10-4 mA/mm.
The engineers have also built an AlGaN/GaN HEMT voltage amplifier circuit with a silicon current source. Fed with a 3 V supply, this amplifier delivers a gain of 17. Goals for the team are to scale the process to 8-inch wafers and work with circuit designers to develop hybrid circuits based on GaN and silicon.
H.-S. Lee et al. Electron Device Lett. 33 200 (2012)
