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InGaAs Nanowire Transistors Outstrip Silicon

Researchers have developed a novel, vertical transistor that outperforms typical MOSFETs. Compound Semiconductor talks to the Japanese team behind the device that promises to deliver smaller, faster electronics.


Japan-based researchers have fabricated a vertical transistor, comprising III-V nanowires stacked on a silicon substrate. The device performs better than conventional planar MOSFETs and looks set to deliver the scaled-down electronics of the future.

Over the past decades, conventional microelectronics have become smaller and smaller as chip designers race to cram more transistors onto the silicon chip. However, as transistors continue to shrink, performance problems have surfaced and the devices are no longer the clean on-off switches they once were.

With the distance between a transistor's source and drain down to mere nanometres, current leakage between the two terminals is a massive problem. To plug the leak, researchers have raised the transistor's channel, source and drain out of the substrate, devising three-dimensional multi-gate transistors, such as the FinFET, with vertical architectures.

But while the likes of Intel and IBM integrate the latest silicon architectures into devices, researchers now hope to fabricate structures from compound semiconductors to boost performance even more.

The Japan-based Research Center for Integrated Quantum Electronics, Hokkaido University, is home to one such group. Here, Katushiro Tomioka, and colleagues, have spent several years trying to integrate vertically aligned InGaAs nanowires onto silicon. In 2009, they unveiled a technique to selectively grow GaAs nano-wires on silicon, and have recently fabricated high performance vertical transistors, based on a novel surrounding-gate architecture.

Here the actual transistor gate is wrapped around vertically-aligned InGaAs nano-wires, to better resist short channel effects, such as leakage. And this, asserts Tomioka, is where the future of transistors lies.

“The gate-architecture in mature Si-CMOS technologies has already changed from planar to Fin-gate, and sooner or later will move onto the surrounding gate architecture," he says. “Silicon channels will be replaced by InGaAs and Ge channels... and as Intel has suggested, heterogeneous integration of group III-V materials will become the basis of lower power and high speed CMOS."



To fabricate the vertical transistors, the researchers first grew an array of ten InGaAs nanowires on a silicon substrate. They heat-treated the substrate in an arsine atmosphere to replace the outermost silicon atoms with arsenide atoms, ready for nanowire growth. A silicon dioxide film was deposited onto the substrate surface with circular openings then formed on the film, using electron-beam lithography and wet chemical etching. Nano-wires were grown onto the openings, via metal-organic vapour phase epitaxy.

“So far, nano-wires have been grown by a vapour-liquid-solid method, but this cannot control their position," explains Tomioka. “We've used selective area growth, with position-defined masks... to align and integrate the nanowires onto the substrates."

Each nanowires was then coated with a hafnium oxide-based film and sputtered with tungsten metal to form the gate. By spin-coating the nanowires with a benzocyclobutene polymer (BCB), and using reactive ion etching to etch back the BCB, tungsten gates and hafnium-based film the researchers isolated the gate and drain regions. Lastly, a metal drain and source were deposited onto either end of the structure to form the transistor.

Crucially, the fabrication process reduced the lattice mismatches between the silicon substrate and InGaAs nanowires, that can lead to crystallographic defects and degrade device performance. And while switching characteristics beat those of previously-built nanowire surrounding gate transistors, the researchers knew the device would have to perform better to satisfy the demands of next-generation electronics.

With this in mind, they went on to fabricate a similar device, but this time using “core-multishell nanowires", in which layers of InP, InAlAs and InGaAs are grown around an InGaAs core. The results have been startling.

Not only does this transistor have a greatly increased on-state current and transconductance, compared to the original InGaAs-on silicon device, but device performance is better than that of your typical MOSFET. Having obtained these extremely high performances, the researchers now intend to fabricate a p-type field-effect-transistor using the same nanowires.

“Our research will be a milestone in the history of semiconductor applications," concludes Tomioka. “These devices will have the performance necessary for use in future silicon transistor technology."



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