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Using Monolayers To Create P-n Junctions In Graphene

New developments using graphene are suited for use in field-effect transistors. But if researchers are able to lower the temperature, they may be able to use graphene in optoelectronic products
The electronic properties of graphene films are directly affected by the characteristics of the substrates on which they are grown or to which they are transferred.

Researchers are taking advantage of this to create graphene p-n junctions by transferring films of the promising electronic material to substrates that have been patterned by compounds that are either strong electron donors or electron acceptors.

Georgia Tech postdoctoral fellow Hossein Sojoudi holds a wafer containing graphene p-n junctions, while the screen display in the background shows electrical data measured in the devices. (Credit: Gary Meek)

A low temperature, controllable and stable method has been developed to dope graphene films using self-assembled monolayers that modify the interface of graphene and its support substrate. Using this concept, a team of researchers at the Georgia Institute of Technology has created graphene p-n junctions - which are essential to fabricating devices - without damaging the material’s lattice structure or significantly reducing electron/hole mobility.

The graphene was grown on a copper film using CVD, a process that allows synthesis of large-scale films and their transfer to desired substrates for device applications. The graphene films were transferred to silicon dioxide substrates that were functionalised with the self-assembled monolayers.

“We have been successful at showing that you can make fairly well doped p-type and n-type graphene controllably by patterning the underlying monolayer instead of modifying the graphene directly," says Clifford Henderson, a professor in the Georgia Tech School of Chemical & Biomolecular Engineering. “Putting graphene on top of self-assembled monolayers uses the effect of electron donation or electron withdrawal from underneath the graphene to modify the material’s electronic properties."

Creating n-type and p-type doping in graphene , which has no natural bandgap, has led to development of several approaches. Scientists have substituted nitrogen atoms for some of the carbon atoms in the graphene lattice, compounds have been applied to the surface of the graphene, and the edges of graphene nanoribbons have been modified. However, most of these techniques have disadvantages, including disruption of the lattice – which reduces electron mobility – and long-term stability issues.

“Any time you put graphene into contact with a substrate of any kind, the material has an inherent tendency to change its electrical properties," Henderson says. “We wondered if we could do that in a controlled way and use it to our advantage to make the material predominately n-type or p-type. This could create a doping effect without introducing defects that would disrupt the material’s attractive electron mobility."

Using conventional lithography techniques, the researchers created patterns from different silane materials on a dielectric substrate, usually silicon oxide. The materials were chosen because they are either strong electron donors or electron acceptors. When a thin film of graphene is placed over the patterns, the underlying materials create charged sections in the graphene that correspond to the patterning.

“We were able to dope the graphene into bothn-type and p-type materials through an electron donation or withdrawal effect from the monolayer," Henderson explains. “That doesn’t lead to the substitutional defects that are seen with many of the other doping processes. The graphene structure itself is still pristine as it comes to us in the transfer process."

The monolayers are bonded to the dielectric substrate and are thermally stable up to 200 degrees Celsius with the graphene film over them, Sojoudi, a postdoctoral fellow working on the project, notes. The Georgia Tech team has used 3-Aminopropyltriethoxysilane and perfluorooctyltriethoxysilane for patterning. In principle, however, there are many other commercially-available materials that could also create the patterns.

Clifford Henderson’s face is reflected in a wafer containing graphene p-n junctions. The screen in the background shows electrical data measurements. (Credit: Gary Meek)

“You can build as many n-type and p-type regions as you want," Sojoudi says. “You can even step the doping controllably up and down. This technique gives you ontrol over the doping level and what the dominant carrier is in each region."

The researchers used their technique to fabricate graphene p-n junctions, which was verified by the creation of field-effect transistors (FETs). Characteristic I-V curves indicated the presence of two separate Dirac points, which indicated an energy separation of neutrality points between the p and n regions in the graphene, points out Soujoudi.

The group uses CVD to create thin films of graphene on copper foil. A thick film of PMMA was spin-coated atop the graphene, and the underlying copper was then removed. The polymer serves as a carrier for the graphene until it can be placed onto the monolayer-coated substrate, after which it is removed.

Beyond developing the doping techniques, the team is also exploring new precursor materials that could allow CVD production of graphene at temperatures low enough to permit fabrication directly on other devices. That could eliminate the need for transferring the graphene from one substrate to another.

A low-cost, low-temperature means of producing graphene could also allow the films to find broader applications in displays, solar cells and organic LEDs, where large sheets of graphene would be needed.

“The real goal is to find ways to make graphene at lower temperatures and in ways that allow us to integrate it with other devices, either silicon CMOS or other materials that couldn’t tolerate the high temperatures required for the initial growth," Henderson says. “We are looking at ways to make graphene into a useful electronic or optoelectronic material at low temperatures and in patterned forms."

Further details of this work has been published in the paper, "Creating Graphene p-n Junctions Using Self-Assembled Monolayers," by Sojoud et al in ACS Applied Materials & Interfaces, and the publication, "Facile Formation of Graphene P-N Junctions Using Self-Assembled Monolayers" by Baltazar et al in The Journal of Physical Chemistry C,

Funding for the research came from the National Science Foundation, through the Georgia Tech MRSEC and through separate research grants.

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