If reductions in the dimensions of the transistor are going to go hand-in-hand with increases in its performance and a trimming of its power consumption, silicon channels will have to be replaced with higher mobility materials, such as III-Vs. But will this happen, and if so, when? What has to be done to usher in these new materials? And if III-Vs are to make an impact in microprocessors, will they be there to stay? Richard Stevenson puts these questions, plus several more, to analyst Dean Freeman from Gartner Research.

Q Will silicon CMOS prevail for many decades? Or are there barriers to scaling with silicon?

A I think you’ve got to help the silicon. Silicon as a template is going to be what we use for a long time, but the gate material is probably going to evolve. We’ve gone from a planar, metal oxide and silicon semiconductor to a high-k, metal gate transistor. You are probably going to get to the point where you have some sort of compound semiconductor as part of the gate material.

You can probably shrink silicon down to the 4-nanometre technology node and even shrink the transistor further than that. The question is how much power is it going to take to turn the transistor off and keep it off. Based on the technology and the way we understand it now, you’re going to have a very leaky device for anything made out of silicon.

Guys from Soitec are saying that they can help out a little bit, but there is only so much that leaks through the bottom of the transistor. You also have leaks from the source to the drain, and from the substrate into the gate. So you eventually end up at a point where you just have to have so much power that it is not economical to run the device. Many years ago Patrick Gelsinger [CEO of VMware] showed the slide that we will go from having an iron on our lap to a nuclear power plant on our lap. That will continue to happen with new materials. However, [the extent of this heating] depends on what type of material you get in the gate, as well as what you can do to keep the leakage at a minimum as you continue to shrink the devices.

Q Do many within the silicon industry believe that other materials are needed for the channel?

A Right now, a lot of different materials are being looked at for the channel. You’ve got germanium for the pFET, indium antimonide arsenide for the nFET; you’ve also got graphene and nanotubes being looked at; and you have folks looking at different types of silicon nanowires. So there are a lot of different irons in the fire.
The question is this: When we get down to the point where we can no longer make the high-kmetal gate transistor work, what is next? What can we manufacture at a reasonable cost so we can keep providing faster-working devices at a lower cost?

Q One of the most radical changes in the history of the silicon industry is the move in the last few years from a planar device to one with a fin protruding out of the surface. If new materials are introduced, will they be in the form of finFETs, or could we see a return to planar devices?

A It depends on the mobility of the device. One advantage of a fin device is that you get so much higher mobility, because you have gone from having just one surface that the electrons can pass through to what I call two-and-a-half, based on  the height and width. This basically doubles the mobility of the device.

If we get something such as indium antimonide phosphide or graphene, which both have a really high mobility, it is possible that we could go back to a planar device. That would ease some of the manufacturing difficulties a little bit. But it’s likely that the fin is here to stay, provided that the fabs can continue to manufacture it. That has to do with lithography and etching.

Q If III-Vs and germanium are to make an impact, when do you believe this will be?

A The rumour is that germanium is going to show up at the Intel 10 nanometre technology node. So, that will show up at what the foundry is now calling the 7 nanometre technology node. So you will probably see the III-V materials at the Intel 7 nanometre technology node. You could see the foundries try to accelerate this, but Intel, from a research and development perspective, is significantly ahead of most of the foundries.

Samsung’s and Global Foundries’ ace-in-the-hole is the work that they have got going with IBM − IBM has been playing with weird materials for a long time. I don’t think that they’d be able to leapfrog Intel, but they could potentially introduce a III-V transistor in a very similar timeframe. However, when would the foundries be able to economically push that out to their customers?

Q One of the challenges with III-Vs is uniting them with silicon in a manner that could be deployed in high volume, high-yield foundries. imec is pioneering the growth of III-Vs in trenches formed in silicon wafers, while IBM is looking at a wafer-bonding approach. Are there other promising options?

A It appears that you can grow nanowires, either in a vertical or a horizontal direction. You could drop a trench in, put your catalyst on the side, and then grow these nanowires across a trench. That means that you’ve got a gate-all-around process. I think that’s one of the more probable techniques that you’ll see come out. [That’s because] if you are growing directly on silicon, without the catalyst, you have to start with a buffer layer, so you get the right crystal structure. It appears that you can grow a pretty good nanowire − with the right characteristics − across that trench, without any significant preparation. The only problems are getting the right angle for the nanowires, and making sure that they haven’t gone wild. You want something that’s nice and orderly, verses something that looks like a bunch of earthworms. That’s the technique that they need to iron into perfection.

I haven’t confirmed this, but I’ve heard that although you can grow the nanowires vertically, you can’t make a device out of them, because you can’t do the source-drain properly. This is unfortunate, because growing the nanowires vertically would be the easiest. But if we look at Intel’s technology roadmap, we have 6 years or so until they need to be in production, so we could figure something out between now and then.

Q Are the equipment manufacturers gearing up for anymove to introducing III-Vs into the channel?

A Aixtron and Veeco are talking and making noise about this, and Applied Materials and ASMI are looking at it closely, because it is the next epitaxial material that we are going to have to look at. The University of Illinois has been playing with this stuff for years, and they’ve been working with Intel. And you’ve got IQE: They’re making noise about this, and are capable of doing this as a bulk epitaxial film.

The problem is that there is a lot of risk. You are looking at something that is six years away from production, and you don’t want to jump on the bandwagon with too much money in your pocket.

It was easier with silicon. The move to the high-kmetal gate was a very obvious transition. People had been working with the high-k’s since the 1980s, and everyone knew that you had to make the transition. However, if you take a look at the companies that jumped on-board from a dielectric perspective, there were really only Genus and ASMI, and it took a long time for that move to become economically feasible for them. So the equipment manufacturers are approaching it with a great deal of caution. They want to make sure they do it right, verses doing it several times.

Q If we do move to all III-v channel, it will have implicationsfor other parts of the transistor, such as a new gate stack Is that going to introduce difficulties?

A Not really, because you are still going to use some form of dielectric. If I grow my indium-antimony-based material, I will probably still use a high-k dielectric and I just have to make sure that my interfaces work OK. Actually, my interfaces will probably be better with indium antimony than they are with silicon dioxide. With silicon dioxide, if any oxygen diffuses, I get a thicker or a lower-k dielectric.

It is possible that we could go to a kinder and gentler high-kdielectric, such as alumina, or zirconium, instead of hafnium.

Q There will be concerns within the silicon industry that III-Vs could lead to arsenic contamination within the lines. How big are these concerns?

AYou already use arsenic, antimony and phosphorous as implant dopants in certain applications. So it’s not a huge concern. You build a special room for it and take precautions.



Intel leads the way with the development of new materials and processes to maintain the march of Moore’s law. The company is tipped to introduce germanium at its 10 nm node, and possibly follow this up with III-Vs at the 7 nm node. Credit: Intel

Q Are there other concerns that those in the silicon fabs have?

A I don’t think we are far enough along yet for those concerns to have manifested themselves. As Intel would say, we are still in path finding.
With germanium, you are going to have new process techniques. You are going to etch it slightly differently, you are going to have to deposit it slightly differently, and it’s a lower temperature process, so you will have to adapt to those new materials, just like we had to adapt to the high-kmetal gate process. 

With an indium antimony arsenide process, you’ll have to be careful not to crank your temperature up too much, or you’ll loose some of the favourable dopants and you could shift your threshold voltage as a result of out-gasing of one of those III-V materials. 

Q How long could III-Vs make an impact for?

A That’s very hard to say. My guess is that it is hard to conceive that you would go through all the work it would take to introduce a new material for just one generation. I think that’s part of the concern that is going into the decision-making process. The one great thing about the indium antimony scheme is that this is the second fastest material in the world, behind graphene and carbon nanotubes. So you could probably get two-to-three generations out of it.

A big question is how much further can we shrink what I call conventional process technology? Right now, everything is ‘you dep, you print, you etch’. We have a pretty clear path to 7 nanometres, and there we will probably see our first III-V materials.

Once we go beyond 7 nanometres it gets a little fuzzier. We are adding new materials, we’ve got some challenges with lithography, and it’s not as clear what we have to do to get the power-performance that we’ve been used to for the last 40 years.

Once you start to get down to 5 nanometres or 3 nanometres, you are probably going to have to see self-assembly introduced for the very small features. You will also have some difficulties in the metallisation scheme. An engineer might be saying that they’ve got this transistor that is fantastic, but its copper metallisation doesn’t work fast enough and its resistance is too high.

Aside from having to deal with the transistor, you have to deal with the interconnect as you move down to these smaller and smaller technology nodes. There is some thinking about how to get around this, with graphene and carbon nanotubes, and doing some different things with the copper interconnect, but it will be challenging.

Q Is the future of the channel the biggest challenge facing the silicon industry, or is it the scaling of lithography?

A I think it depends on who you talk to. EUV is a huge challenge. We know we can do 7 nanometres with optical lithography – it just gets very expensive. Now, when EUV comes on-board, it reduces the expense of lithography. But once we get past 7 nanometres to 5 nanometres, you then have to start playing some of the same tricks with EUV that you were playing with optical lithography, such as proximity correction, so the lithography costs begin to go up again.

Historically, we’ve had about a 30 percent cost decline per node, and a 30 percent shrink in silicon, with the cost falling as a result of shrinking the silicon. If we continue to stay on that curve, we’ll continue to shrink, but if lithography costs are going up, and transistor material costs are going up, that curve starts to tick up. If you don’t get the performance that you’re looking for, you have to start to question the economics: Is the speed you’re getting out of the device worth going to the next node?

Q So is it not obvious that scaling will continue forever?

A There is grumbling at the foundries that they are not getting the power-performance curves that they need, or historically have gotten. This is why the foundries are trying to jump to the finFET at 20 nanometres as quickly as they can to get back on the power-performance curve. I think you have to look at whether we can continue to stay on that curve. If I can get a newer gadget that can work faster every three years, I’m probably going to continue to spend money on it. If I can’t do it, we’ll be in the PC doldrums we are now, with consumers saying: ‘I used to buy a new PC every three years, but this one works fine. So maybe I’ll just upgrade the screen, so it’s a little bit bigger and a little bit brighter, and I’ll make do with what I have. I have enough storage and it’s fast enough for what I’m doing, and until Microsoft will not support my operating system, I can continue to live. I use it for content creation, so I don’t need the speed, because I’m using my iPhone, my iPad or my tablet for my content absorption, and my PC is a secondary unit for content absorption.’

Tablets are still going pretty strong, but you are starting to see the application fatigue that has been out there in the cell phone. The high-end cell phones aren’t selling. Parents have finally come to the realisation: Why am I buying my child a $200 iPhone when I can give them the 4S for free, or I can get them a cheap Android for free and just pay the monthly fee.

The newness has worn off. But if I am able to, say, take that cell phone and shrink that into a Google glasses or a watch, then I’ll not carry a cell phone with me any more. I’ll have something else for my visual, whether it’s the glasses or watch, and everything is voice recognition, because my processors are fast enough to do that and understand what I say, even if I have a terrible ascent or don’t speak clearly. Then, maybe we’ll continue to drive the new applications or the new toy harder and faster. But if we don’t hit those price points, we’re not going to continue to drive those killer applications.


Dean Freeman, Research Vice-President at Gartner Research,is part of the Semiconductor Equipment, Manufacturing, and Materials service in the Semiconductors group. He is responsible for market research and analysis of semiconductor equipment and trends in IC manufacturing techniques, as well as emerging semiconductor technology, which includes nanotechnology, LEDs and printed electronics. Freeman has almost three decades of experience in the semiconductor industry, having worked with Texas Instruments, Lam Research, FSI International and Watkins-Johnson’s Semiconductor Equipment Group.