Ultra-high Voltage Devices For Future Power Infrastructure
Fast growth of high-quality SiC epilayers has paved the way to the fabrication of power devices with blocking voltages exceeding 20 kV.
By Tsunenobu Kimoto from Kyoto University, Japan
Following research stretching back more than 40 years, shipments of SiC power devices are now significant and rising fast. Two of the biggest sellers are Schottky barrier diodes (SBDs) and power MOSFETs, which are increasingly displacing silicon incumbents and enabling the construction of smaller, more efficient power converters and inverters.
Thanks to this, SiC chips will be winning deployment in power supplies, motor controls, photovoltaic converters, telecommunications equipment, heating, robotics, electric/hybrid vehicles, traction and electric power transmission (see Figure 1). According to several institutes, one impact of this trend is that by 2025, SiC power devices will produce a combined electric power saving exceeding 10 GW – that’s comparable to the power generated by about ten nuclear plants.
Figure 1. Different voltage ratings are required for different applications
Today, a time when the revolution in power electronics is still in its infancy, the operating voltages of commercial SiC diodes and transistors are predominantly in the 600 V - 1.7 kV range. But that’s by no means the limit of what is possible – recent progress in the labs shows that blocking voltages of more than 20 kV are attainable. This opens up the possibility for innovative hardware for electric power infrastructure, advanced traction applications and accelerators of particles, such as electrons and protons.
Devices that combine ultra-high blocking voltages with very low losses can also play a key role in the future of electric power transmission/distribution infrastructure and smart grids. They could feature in distributed power lines, which operate in the 6.6–7.2 kV range, and could be the 13–15 kV power devices required for the construction of single-level converters. Another attractive opportunity for the deployment of ultra-high-voltage SiC devices is in solid-state transformers (see Figure 2). In high-voltage DC power transmission, voltages can be as high as 150–250 kV. Today, a number of 6–8 kV silicon thyristors are stacked in series to provide conversion of electrical power at such high voltages, but this has the downsides of enormous energy dissipation and self-heating. If ultra-high-voltage SiC chips could replace these devices, this would lead to considerable energy savings.
Figure 2. Ultra-high-voltage SiC power devices can enable a substantial trimming of the size and weight of power converters
To help turn this dream into a reality, our team of researchers at Kyoto University has been developing SiC devices that are now setting a new benchmark for high-voltage operation. These chips, which are formed using the high epitaxial growth rates needed for a viable production process, can withstand voltages of almost 27 kV.
Interest in SiC has been driven by its wide bandgap – it is 3.26 eV in the 4H polytype commonly used for making power devices. This wide bandgap is responsible for a breakdown electric field strength ten times that of silicon and a thermal conductivity that is three times that of silicon. Furthermore, SiC is an exceptional wide bandgap semiconductor, which offers the opportunity to control the doping concentration over a very wide range (n-type: 1014 – 1019 cm−3, p-type: 1014 – 1020 cm−3). In addition, SiC devices can operate at high temperatures, such as in excess of 250°C. Drawing on all of these attractive attributes enables the simplification of the bulky cooling units often required in silicon-based power converters.
The higher field strengths permitted with SiC aid device design. Compared to silicon, blocking-layer thickness can be tens times thinner, while the doping concentration can be increased by two orders of magnitude (see Figure 3). Thanks to this, it is possible to realise huge reductions in the voltage-blocking region resistance, and ultimately achieve low levels of power dissipation.
Figure 3. Electric field distributions in one-sided abrupt junction in SiC and silicon are markedly different, even though they have the same breakdown voltages. That’s because: the breakdown field strength for SiC is ten times that for silicon, so the thicknesses of the voltage-blocking layers of SiC power devices can be one-tenth of that in the corresponding silicon devices; and the doping concentration in the SiC devices can be two orders of magnitude higher than that in the silicon counterparts
The tried and tested route for realising a high blocking voltage in any semiconductor device is to increase material thickness and trim doping concentration in the voltage-blocking region. Calculating the impact of these changes is easy, and helps to guide device designers that must also consider the doping-dependent breakdown electric field of the material (see Table 1).
Table 1. Typical thicknesses and doping concentrations required for specific blocking voltages in silicon and SiC devices. Calculations took into account the doping-dependent breakdown electric field of the materials
These back-of-the-envelope calculations also reveal why it is impossible to build a 20 kV device from silicon: the required doping concentration would have to be close to the intrinsic carrier concentration at room temperature, while the required thickness would be impractical. Fortunately, with SiC, it’s an entirely different story – a 20 kV device falls easily within the limits of what is possible.
Manufacturing such a device in high volumes is not out of the question, given the rapid progress in SiC bulk growth processes that has led to the availability of single crystalline SiC wafers of reasonable quality with 100 mm and 150 mm diameters. There have also been remarkable advances in SiC epitaxy and device processing technologies, such as ion implantation and metallization, and, on top of this, it is possible to draw on the development of devices operating at lower voltages. Back in 1991 NASA reported the first 1 kV SiC pindiode, while our group announced the first SiC Schottky barrier diode operating at that voltage two years later, and since then many more groups from all over the world have started to develop high-voltage SiC power devices (see Figure 4 for an overview of the increases in SiC blocking voltage).
Figure 4. The last decade has witnessed a significant increase in blocking voltages of SiC pindiodes
One decision facing designers of power electronic systems and modules is whether to select a unipolar device, such as an SBD or a FET, or deploy a bipolar device, such as a pindiode, thyristor, or insulated-gate bipolar transistor (IGBT). The decision partly depends on the blocking voltage required. An SBD is an attractive option at lower blocking voltages, such as 1 kV, because in this regime it exhibits very good on-state characteristics. However, when the voltage requirement increases to 20 kV, the on-resistance climbs to unacceptable levels (see Figure 5). So, at these ultra-high voltages, the SiC pindiode is a better choice, thanks to the long lifetime of its injected carriers. This long lifetime is due to the indirect band gap and high crystalline quality, and is a key factor for attaining the conductivity modulation effect.
Figure 5. Forward characteristics for a 1 kV SiC SBD, a 20 kV SiC SBD, and a 20 kV SiC pindiode with two different carrier lifetimes (simulated). For 20 kV applications, a pindiode with sufficiently long carrier lifetime is the most promising
However, a long carrier lifetime is not guaranteed in a SiC device. Back in 2007 we identified a carrier-lifetime killer in this wide bandgap material − a deep level, known as a Z1/2 centre, that is located 0.62 eV below the conduction band. But by 2009 we had succeeded in eliminating this defect, an acceptor level of a single carbon vacancy, by thermal oxidation.
This thermal oxidation process leads to the formation of SiO2 on the surface of SiC. But what happens to the carbon? That’s a long-standing and still-open question, but in our view most carbon atoms diffuse out as a form of CO, while a smaller number remain near the SiO2/SiC interface. Here they can even be emitted into the SiC side, where they will diffuse in the bulk region. Carbon vacancies here are filled with diffusing carbon interstitials, ensuring that the lifetime killer is eliminated from the surface right down to deep in the epilayers.
Armed with this this innovative defect-elimination technique, we realised a lifetime of over 30 ms (see Figure 6). Surface recombination is now the barrier to longer lifetimes, which should be in excess of 50 ms. But even with our current values for carrier lifetime, we can realise conductivity modulation of 20 kV devices.
Figure 6. Eliminating defects increases the carrier lifetime in SiC. Lifetimes are revealed by microwave-detected photoconductance decay measurements, which show the improvement in a 220 mm-thick epilayer that results from the defect-elimination process
To ultra-high voltages
Fabrication of 20 kV SiC devices requires the growth of a voltage-blocking layer at least 150 mm-thick and doped to a carrier concentration of no more than low ~1014 cm−3. Such a film can be grown homoepitaxially by CVD at 1650°C on low-resistivity n-type SiC (0001) substrates.
Fast growth rates are very attractive for such a thick layer. In our group, we have successfully increased the SiC growth rate from 10 mm/h to beyond 50 mm/h. This has been accomplished while avoiding issues related to nitrogen donor contamination, by either reducing the growth pressure or increasing the ratio of carbon-to-silicon in the precursor gases. These refinements enable background doping concentrations in the SiC epitaxial layers of less than 1×1013 cm−3, which is sufficiently low for the development of ultra-high voltage devices.
Fabrication of our SiC pindiode involved epitaxial growth of an n-type, very thick voltage-blocking layer, and a highly doped p-type emitter that acts as an anode. Diode isolation followed, using an improved bevel mesa structure with a rounded bottom. To alleviate electric field crowding near the junction edge − which causes the device to breakdown at a much lower voltage than what should be expected from calculations based on thickness and doping concentration − we then employed an Al+ implantation process and subsequent activation annealing to create an appropriate junction termination structure (see Figure 7). After this, we added ohmic contacts for the p-type anode and the n-type cathode from Al/Ti layers and a nickel layer sintered at 1000 °C. Thermal oxidation and deposition of a 4 mm-thick polyimide film passivated the surface and prevented surface arcing. Note that fabrication also involved a thermal oxidation-based lifetime enhancement process, performed after the epitaxial growth of the n-type voltage-blocking layer.
Figure 7. Fabrication of the SiC pindiode involved epitaxial growth of a very thick n-type voltage-blocking layer and a highly-doped p-type emitter, followed by diode isolation that resulted from formation of an improved bevel mesa with a rounded bottom. This alleviates electric field crowding near the junction edge
Alleviating electric field crowding is one of the greatest challenges associated with forming an ultra-high-voltage SiC device. To prevent this from impacting device performance, the structure and the doping profile of the Al+-implanted junction-termination-extension (JTE) region have to be carefully designed and optimised. If the aluminium doping concentration is too low, severe electric field crowding occurs near the mesa edge; but if this doping is too high, crowding is present at the outer edge of the JTE region.
We address this issue with a ‘space-modulated’ JTE structure featuring multiple rings formed inside a reduced surface field-type, Al+-implanted JTE region. By modulating the widths and spacing of individual rings, the effective JTE dose gradually decreases as it progresses toward the outer edge. In turn, this minimises electric field crowding and provides a wide optimum JTE dose range. Device simulations enabled optimisation of the structure and the doping profile of the JTE region (see Figure 8).
Figure 8. Device simulations enabled optimisation of the junction termination structure, which was improved by understanding the electric field strength distribution near the edge of a pindiode under high-voltage (18 kV) reverse bias. The original structure with its multiple space-modulated rings offers reduced electric field crowding near the edge
Our most recent pindiodes have a 260 mm-thick voltage-blocking layer. Mesa diameter and the JTE length are just 300 mm and 1050 mm, respectively – that’s because the aim of producing this diode is to provide a proof of the concept and not a power device capable of handling very high currents.
Device testing involved immersion of the diode in the dielectric liquid Fluorinert, and on-wafer testing with a DC voltage sweep (see Figure 9). Determining device performance is not easy, because no suitable commercial UHV testing systems are available at present, and we had to address several technical issues related to cable connections and the probe configuration to prevent air sparking.
Figure 9. A fabricated diode during high-voltage testing
Our devices can withstand voltages up to 26.9 kV (see Figure 10), the limit of our measurement set-up, and they set a new benchmark for any solid-state device. We estimate that the real breakdown voltage is more than 30 kV, but we will only be able to prove this after improving our measurement system. On-resistance of this diode is just 19 mW cm2, compared with 430 mWÊcm2 for a SBD (no carrier injection) processed on the same wafer without a p-type anode. This pair of results underlines how the conductivity modulation effect can slash the resistance of a very thick, lightly-doped layer. The original carrier-lifetime enhancement technique has helped to realise a low on-resistance in our devices. Analysing the resistance components with our test-element-group characterisation tool indicates that the contact resistivity of the anode contact is approximately 4–5 mWÊcm2. This indicates that further improvements in on-resistance could result from increasing the acceptor concentration in the anode’s top layer and optimising the process.
Figure 10.Current density-voltage characteristics of a mesa SiC pindiode with a space-modulated JTE structure (total JTE length of 1050 mm). The voltage-blocking layer is 260 mm-thick and doped to a density of 1×1014 cm-3. At a reverse voltage of 26.9 kV (the limit of our measurement set-up), this diode did not exhibit breakdown
One of our next goals is to eliminate basal-plane dislocations in SiC. These imperfections, which lead to carrier-recombination-induced dislocation glide that can in turn create Shockley-type stacking faults, degrade device performance: on-resistance and leakage current both increase. In our latest devices, the device area is typically just 2–3 mm in diameter, including the termination region. But if this class of device is to be considered for electric power infrastructure, its area will need to increase to more than 1 cm2, so that it can handle currents far greater than 100 A. The density of basal-plane dislocations in our latest SiC epitaxial layers is in the 0.1–3 cm-2 range, and this must be plummet to below 0.01 cm-2 to enable high-yield production of devices with high current-handling capabilities.
Another target is the development of 20 kV-class power-switching devices, such as thyristors, IGBTs, and bipolar junction transistors (BJTs). We have started with a preliminary study on UHV BJTs, demonstrating a 21 kV BJT with a current gain of 63. Now we will try to improve the performance of these devices, while undertaking trials to fabricate other types of UHV power switching device.
The author would like to acknowledge J. Suda, H. Miyake, H. Niwa, T. Okuda, N. Kaji, and S. Ichikawa from Kyoto University for their contributions to this study.
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