News Article

Mastering The Marriage Of III-Vs And Silicon

Defect-trapping pockets enable the growth of high-quality films of GaAs on large-area, conventional silicon substrates 

IN 1965, GORDON MOORE at the time director of research and development at Fairchild Semiconductor, published a now-famous article in Electronics. In his four-page piece he outlined the benefits wrought from shrinking the dimensions of silicon transistors, and how fast this level of miniaturization might occur. Hindsight highlights the greatness of Moore's insight, which has been captured by a law named after him.

It is now just over fifty years since the publishing of Moore's seminal paper. And for most of that time, by simply scaling device dimensions, engineers have delivered gains in speed and cost while trimming the power required to operate each transistor. But recently, shrinking device size has not been enough âˆ' introducing new materials has held the key to maintaining improvements in performance while trimming dimensions. In this regard, the biggest modification so far has been the shift from SiO2 to high-K HfO2 as gate dielectric, to prevent leakage currents from escalating to unacceptable levels when the thickness was scaled to a few angstroms.

This revolution in the range of materials employed within the transistor is driving a new era for digital and memory devices. The age of "˜more-than-Moore' has arrived. This is a time when both new materials and three-dimensional non-planar architectures are viewed as the way forward. There is also the promise of system-on-chip solutions that dramatically improve capability, while trimming size, cost and power dissipation. 

Advances in "˜more-than-Moore' will require the heterogeneous integration of broad classes of materials that are traditionally not present in silicon fabs. Silicon is great for electronic switching and memory, but its indirect bandgap precludes its use in efficient light emission and photon interaction. This weakness is a major flaw in the "˜big data' era, where there is explosive growth in demand for data transmission. But hopefully silicon's deficiency can be addressed by integrating it with photonic semiconductors, such as III-Vs. Such a marriage could revolutionize future on-chip and chip-to-chip communication technologies with optical interconnects.

The most attractive option for bringing these two classes of material together is to grow an epitaxial III-V film on a silicon substrate. There are challenges associated with this, primarily arising from differences in the lattice and thermal mismatch and crystal polarity. Attempts to succeed in this endeavour date back to the 1980s, but despite a great deal of effort by researchers from all around the globe, progress has been slow, and breakthroughs few and far between. 

One group that has made significant strides in this direction is our team from Hong Kong University of Science and Technology (HKUST). We are exploring technologies for growing III-V nanostructures and thin films on CMOS-compatible silicon substrates by MOCVD. We are by no means alone in pursuing this approach. However, while most groups are using catalysts and focusing on vertically orientated nano-structured materials, we are working on compliant substrates, which are highly compatible with the well-established silicon planar processing technology. Our great strength is that we can close the gap between the material growth schemes and the ultimate device implementation.

Our efforts can be traced back to the 2000s, when we first took the lead in the metamorphic growth of InP on planar (001) silicon substrates. Instead of using conventional techniques such as compositional grading of III-V alloys or a germanium buffer, we developed a two-temperature growth process and optimized intermediate GaAs buffers.  We overcame the problems associated with an 8 percent lattice mismatch, and achieved device-quality InP featuring a smooth surface. This led to the demonstration of InAlAs/InGaAs based HEMTs and MOSHEMTs on planar silicon. Both of these types of device exhibit state-of-the-art characteristics.

A two-pronged attack

To further improve the material crystal quality, we have adopted a hybrid approach to forming III-Vs on silicon. We combine selective-area heteroepitaxy with epitaxial lateral overgrowth, which is undertaken on nanometre-scale, patterned silicon substrates. One of the strengths of using this particular form of substrate is that it allows the use of recessed pockets âˆ' designed correctly, they offer a unique, defect-trapping capability that is not possible with conventional blanket heteroepitaxy.

Taking this approach, we produced ultra-low-defect antiphase-domain-free GaAs thin films on silicon. These were formed via deposition on highly ordered in-plane GaAs nanowires on V-grooved silicon.

To produce these GaAs films, we began by taking planar silicon (001) wafers, and patterning them with [110]-orientated SiO2 stripes with a line-opening width of 90 nm and a line pitch of 130 nm. This created regions in the silicon substrate with a shallow recess, which defines the defect-containing silicon pockets. This approach is notably different from traditional blanket heteroepitaxy, which does not employ the exactly orientated substrates that we use, but rather off-cut silicon, which minimises the formation of anti-phase domains.

We avoid anti-phase domains by etching V-shaped grooves at the bottom of the trenches. This technique, which has been demonstrated by a team of researchers from imec, Belgium, enables the deposition of III-V materials on exposed {111} silicon facets. On these side walls, the films that form tend to be free from anti-phase domains.

By adopting a two-step growth method for the epitaxy of planar GaAs nanowires on V-grooved silicon, we are able to realise a superior crystalline quality (see Figure 1 (a)). After thermal cleaning at 800°C in an MOCVD chamber, we begin by depositing a GaAs nucleation layer at 385ËšC. This is followed by the growth of a GaAs main layer at typically 550ËšC. 

Strengths of our highly-ordered, site-controlled GaAs nanowires, which are separated by SiO2, include smooth facets and uniform morphology (see Figure 1(b)). Analysis of X-ray diffraction Ï‰-rocking curves indicates that nanowires with a thickness of 150 nm yield a full-width-at-half-maximum that is comparable to that of 1 Âµm-thick GaAs thin films on planar off-cut silicon. In other words, switching from planar growth to our novel defect reduction approach slashes buffer thickness by more than a factor of six for the same crystalline quality.

Scrutinising our structures with cross-sectional transmission electron microscopy uncovers some peculiar defect-trapping phenomena (see Figure 2 (a)). Close examination of the GaAs-silicon hetero-interface reveals that the 4.1 percent lattice mismatch is not accommodated by propagation of threading dislocations, but by formation of stacking-disordered layers just a few nanometers thick (see Figure 2 (b)). Thanks to this novel strain-relief mechanism, the GaAs bulk layer has a high crystalline quality, as evidenced by the selective diffraction pattern taken at the apex region (see Figure 2(c)).

Figure 1: (a) Gas flow and temperature sequence for planar GaAs nanowire growth on silicon using a two-step procedure. The precursors that are used are triethylgallium (TEGa) and tertiarybutylarsine (TBA) (b) tilted-view scanning electron microscopy image of planar GaAs nanowires on silicon. 

Figure 2: (a) Cross-sectional transmission electron microscopy image of GaAs nanowires; (b) high-resolution transmission electron microscopy image of the GaAs-silicon interface; (c) selective diffraction pattern taken at the apex of the nanowires; (d) transmission electron microscopy image of the stacking faults trapped by a "˜tiara'-like structure made of silicon.

A tremendous tiara

Looking more closely at the glide of the few-layer stacking faults at the GaAs-silicon hetero-interface reveals that the disordered layers are stopped by a "˜tiara'-like structure (see Figure 2(d)). This is made of silicon beneath the SiO2 walls, and it originates from silicon recessing by combined dry etching and potassium hydroxide wet etching. 

Blocking of defects by this type of hetero-epitaxial approach is often referred to as aspect ratio trapping (ART), or the epitaxial necking effect. Although research on ART is not new, it has traditionally focussed on the growth of high-quality crystals in small cavities, which are defined by a patterned dielectric. There have also been a handful of attempts to produce large area planar films by combining ART with epitaxial layer over-growth. However, the dielectric patterns have spawned hard-to-control asymmetries and irregularities in faceted growth regions. The upshot is a high density of coalescence defects, a rough surface morphology and even more defects originating from the dielectrics. 

Figure 3: (a) Cross-sectional scanning electron microscopy of a 300 nm coalesced GaAs film using the nanowires as a special buffer; (b) transmission electron microscopy image showing that stacking faults at the hetero-interface are localized and trapped by silicon pockets; (c) transmission electron microscopy image highlighting the defect trapping effect by patterned silicon after coalesced thin-film growth.

Our films do not suffer from the same fate, because our tiara-like structure enables the diamond-shaped silicon  pocket to localise and confine most of the hetero-interface defects. Another way to look at this is that by removing SiO2, our nano-sized wires coalesced into planar thin films with a smooth surface, while retaining the defect trapping capability associated with the epitaxial necking effect. 

Removing SiO2 between the merging nanowires improves the surface morphology of the resulting planar thin films. According to images obtained by scanning electron microscopy, just 300 nm of GaAs overgrowth is needed to realise a flat surface (see Figure 3 (a)). Further inspection of the structure by transmission electron microscopy reveals that the silicon pockets can prevent interfacial defects from extending into the upper layers (see Figure 3(b) and (c)). Meanwhile, atomic force microscopy uncovers a surface roughness of 1.9 nm across a 5 µm by 5 µm scan area, and shows that the surface is free of antiphase-domain boundaries (see Figure 4). 

Figure 4: Atomic force microscopy image of a 300 nm-thick coalesced GaAs film grown out of high-ordered nanowires.

We have assessed the crystalline quality of the coalesced GaAs films with X-ray diffraction. Peaks from Ï‰-rocking curves have a full-width at half-maximum that decreases from 230 arcsec to 154 arcsec as the thickness of GaAs increases from 1 µm to 2 µm. The w-2ᶿ linewidth is 72 arcsec. These values indicate good material. 

One way to look at the success that we have had is that compared to GaAs films grown on non-patterned, off-cut silicon, the X-ray linewidth is cut by more than 50 percent with the same buffer thickness. Alternatively, a comparable X-ray linewidth is possible with a three-fold reduction of buffer thickness (see Figure 5).

Figure 5: Comparison of the full-width at half-maximum of X-ray diffraction ω-rocking curves for GaAs thin films grown on non-patterned, off-cut silicon and V-groove patterned silicon substrates.

Characterising our structures demonstrates that the benefits of our growth scheme are not limited to removing the need to use off-cut silicon to suppress anti-phase domains âˆ' they also include a superiority over traditional blanket hetero-epitaxy, when it comes to trapping and reducing defects. What's more, our efforts show that low-defect-density GaAs can be deposited on silicon without the need for other intermediate buffers, such as those based on germanium or graded SiGe.
Additional improvements in the crystalline quality of our as-grown GaAs films are possible by introducing other defect reduction techniques. For example, undertaking three-cycle thermal annealing on 1 µm GaAs on V-grooved silicon cuts the full-width at half-maximum of the w-rocking curve from 230 arcsec to 180 arcsec.

Another lever for increasing material quality is the nanowire pitch size. Get this right and the overall defect density in the coalesced films can be further reduced in the epitaxial layer overgrowth process. Note that if the lateral overgrowth distance is too long, it introduces coalescence defects and increases surface roughness.

For each material one would expect that the optimal growth conditions and the shape of the silicon pockets could be different. We are now looking at materials with an even larger lattice mismatch with silicon, such as InP, because this combination would enable the fabrication of long-wavelength lasers and HEMTs on silicon. These efforts have already led to some success âˆ' we have produced some InP-on-silicon compliant substrates. 

Further opportunities for our technology are associated with using our epitaxial planar nanowires to construct a wide variety of heterostructures on industrial-standard (001) silicon substrates.

Combining these nanostructured materials with a nanofabrication process should provide opportunities to develop novel devices and improve and refine conventional devices in three-dimensional geometries. 

Using the nanowire as a starting point for forming micro-scale crystals and large-area thin films should unlock the door to the fabrication of a range of devices on large-area, inexpensive and abundant silicon substrates. They include those requiring thick hetero-epitaxial layers, such as monolithically integrated quantum dot lasers, detectors and multi-junction solar cells. If our work kicks-starts a global effort in this direction, it may also light a path towards the long-dreamed-of convergence of electronics and photonics on a common platform.

AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.



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