Info
Info
News Article

Slashing Power Consumption With Tunnel FETs

News
Tunnel FETs are the post-CMOS solution, thanks to their ability to deliver great performance while consuming very little power 
BY RAHUL PANDEY AND SUMAN DATTA FROM PENNSYLVANIA STATE UNIVERSITY AND THE UNIVERSITY OF NOTRE DAME

THE SILICON MOSFET is the workhorse of today's semiconductor industry. Through relentless shrinking of its dimensions and steady reductions to its operating voltage, this transistor has driven phenomenal gains in IC performance and device efficiency over several decades. 

This state of affairs can't last, however. The benefits wrought by reducing the size of the transistor, which are detailed in Moore's law, are now under threat. If the operating voltage of today's transistors is trimmed a little more, this would lead to an unacceptable drop in transistor performance. Or to look at it a different way, if the threshold voltage of the silicon MOSFET were reduced to enable a scaling of the operating voltage, there would be an exponential increase in the off-state current, and a corresponding explosion in energy loss. This is a big deal for circuit designers, because the sub-threshold leakage power is as significant as the active power in microprocessors.

The high sub-threshold leakage power stems from the inability of the MOSFET to provide steep switching from the on-state to off-state (see Figure 1(a)). Consequently, even when the MOSFET is turned off, there is a significant leakage current. 

One way to assess the switching ability of the MOSFET is to determine its switching slope, which is defined as the change in gate voltage needed to produce a decade change in drain current. To achieve a limited improvement in the switching slope and improve electrostatistics, there has recently been a change in the transistor architecture from a planar design to a three-dimensional finFET. These newer devices, which feature a fin protruding out of the plane of the wafer, made their commercial debut in 2012 at the 22 nm node, with those at the 14 nm node following in 2014.



Figure 1. A comparison of the incumbent technology, the MOSFET, and a possible successor, the tunnel FET: (a) switching characteristics, and (b) the source-channel carrier-injection mechanism. Filtering of high-energy carriers in the tunnel FET produces sub-KT/q switching slope, which holds the key to reducing the power consumption of the device.

Although the new three-dimensional architecture has bought the silicon industry more time, there is no escaping the fundamental limitations on the switching slope for the MOSFET âˆ' it is related to a Boltzmann distribution describing the energy of carriers in the source region that are emitted thermionically over the barrier. This Boltzmann tyranny in the MOSFET, which restricts the switching slope to 60 mV/decade at room temperature, has driven efforts to look at alternative devices delivering steeper switching. These potential successors could extend supply voltage scaling without compromising leakage power and performance.

Researchers pursuing this goal are not solely focused on a quest for lower voltage, but are also concerned with transport enhancement. To succeed on both fronts, they are investigating the likes of novel materials, strain and bandgap engineering. Within this effort, one device that is piquing the interest of many is the tunnel FET. It promises to deliver switching that is steeper than an optimised MOSFET.

Our team at Pennsylvania State University and the University of Notre Dame is developing a tunnel FET for maintaining the march of Moore's law. We have already had tremendous success, with highlights including the first demonstration of an all III-V system based on complimentary hetero-junction tunnel FETs that can operate at a low voltage and deliver a record-breaking current and switching performance. Our n-type tunnel FETs feature an InGaAs channel and a low density of interface traps, and our p-type tunnel FETs combine a significantly improved interface with a GaAsSb channel.

We have devoted a great deal of effort to developing and refining tunnel FETs, because they have the potential to deliver superior switching to MOSFETs, due to an improvement in the manner in which carriers are injected into the channel (see Figure 1(b)). In a MOSFET, modulation of the gate adjusts the source-to-channel energy barrier, and this controls the thermionic emission of carriers into the channel region. In contrast, with a tunnel FET, carrier injection into the channel comes from inter-band tunnelling from the source to channel region. The great merit of interband tunnelling is that it filters out the high-energy carriers in the Boltzmann distribution that are present in the valence band of the source region. Thanks to this carrier "˜cooling', switching in the tunnel FET is very steep, enabling this device to get far closer to the behaviour of an ideal switch than a MOSFET can.

With a tunnel FET, careful selection of the material system is needed to ensure that when this device is operated at a very low voltage, it outperforms a MOSFET. The natural choice of material for making a tunnel FET is silicon, due to its high-quality native oxide, and the opportunity to produce the device in a state-of-the-art foundry. Silicon's native oxide enables a high-quality interface with a low density of interface states "“ it is 1011 cm-2 eV-1 or less "“ and due to this, many groups have been able to report a device with very steep switching. However, these transistors suffer from a very low on-current, due to the large effective height of the tunnel barrier seen by carriers tunnelling from the source to the channel. This current is so low that it rules out the use of silicon tunnel FETs for logic applications. 


Figure 2. An attractive candidate for enabling a reduction in operating voltage of future logic circuits is complementary p-type and n-type hetero-junction tunnel FETs formed with a common metamorphic buffer technology.

Turning to other semiconductor materials is no guarantee of success, either. With all homo-junction tunnel FETs there is a uniform bandgap in the source, channel and drain regions. This means that the effective height of the barrier equals that of the bandgap. The on-current can be increased by reducing the bandgap, but the price to pay for this is the aggravation of parasitic leakage mechanisms "“ they include Shockley-Read-Hall generation-recombination within the reverse biased p-i-n diode, and band-to-band-tunnelling leakage on the drain side.  Off-state leakage rockets as a result, degrading the current on-to-off ratio and leading to a highly diluted switching slope. 

The solution is to switch from a homo-junction to a hetero-junction. With the latter form of FET it is possible to reduce the height of the tunnel barrier beside the source channel junction, while maintaining large bandgaps in every other region. Armed with this architecture, tunnel FETs can realise a high on-current and a steep switching slope.

Several material systems have been explored in the pursuit of a tunnel FET for next-generation logic. Success has not been easy. Devices made with the combination of silicon and SiGe, and germanium and GeSn, suffer from a significant trade-off between on-current and the switching slope. To implement energy-efficient complementary logic, this trade-off must be addressed while using a material system that is ideally capable of producing high-performance p-type and n-type devices. It is for that reason that we work with arsenide-antimonide hetero-junctions, because they offer a wide range of lattice-matched, compositionally tuneable effective tunnelling barrier heights that are suitable for making n- and p-type tunnel FETs.

One of the biggest challenges associated with making any class of III-V transistor for logic applications is that it is tricky to engineer a high-quality interface between the compound semiconductor channel and the gate dielectric. Native oxides of III-Vs are vastly inferior to those associated with silicon, and this prevents the creation of a pristine interface with the channel.

The problem stems from a III-V surface that is very reactive, with dangling bonds giving rise to a high density of interface states (they can hit 1014 cm-2 eV-1). These imperfections severely limit the ability of the gate field to effectively modulate the source-channel tunnel barrier. In turn, this degrades the performance of the tunnel FET. 

In the last year or so, however, research related to the gate stack has borne much fruit, with interface quality improving, thanks to high-quality surface treatments. These surface treatments consist of a combination of ex-situ wet-etch clean and in-situ pre-ALD H2 or N2 plasma based clean. They provide efficient removal of native oxide along with achieving high-quality surface passivation. Drawing on this success, we have formed InGaAs channel nFETs with excellent interfaces and a low density of interface traps, and p-type GaAsSb siblings with significantly improved interfaces. Our three-dimensional vertical hetero-junction tunnel FET, which is grown by MBE at IQE's facility in Bethlehem, PA, features a metamorphic buffer. This growth technology is used to form our epiwafers because it is capable of forming high-quality, abrupt hetero-junctions. This means that the design of the tunnel, which has been carefully chosen, can be accurately reproduced in the device, with MBE growth forming a defect-free tunnel-interface that maximizes the junction electric field without the need for abrupt doping profiles.

Fabrication of our hetero-junction tunnel FET begins with the creation of nano-pillars. They are formed with an electron-beam lithography patterning process, followed by plasma dry etching. Any damage to the sidewalls caused by dry etching is removed by wet etching to create a structure suitable for self-aligned gate metal deposition at the tunnelling junction.

Gate dielectrics are added by atomic layer deposition. Due to differences in the composition of the channels, n-type devices have ZrO2 gate dielectrics, while p-type FETs have a HfO2 gate. Gate-metal deposition follows, before the source contact for the n-type transistor is defined by electron-beam lithography. Benzo chlorobutane is used as an inter-layer dielectric, which is etched back before a drain contact is deposited on top. For the p-type device, the roles of the source and drain are exchanged.

After these steps, the entire structure is planarized by selective etching of benzo cholorobutane to create vias that enable the addition of contact pads on the top of the inter-layer dielectric. This structure, which has been scrutinised by transmission electron microscopy (see Figure 3), helps to reduce parasitic capacitance.


Figure 3. Cross-sectional transmission electron microscopy of p-type and n-type hetero-junction tunnel FETs.

Forming a good interface between a high-K dielectric and a III-V is particularly tricky for the antimonide-based FET, because movement of the surface Fermi level is restricted by the high density of interface traps near the middle of the bandgap. To overcome this challenge, we undertook a rigorous optimisation of the gate stack. The interface between a GaAs0.35Sb0.65 channel and a HfO2 high-κ dielectric is highly reactive, due to dangling bonds, Sb-Sb bonds, antimonide oxides and anti-site defects. To remove the antimonide-oxides and passivate defect states we combine an ex-situ HCl clean with an in-situ H2 plasma treatment. 

The highest accumulation-capacitance density results from a 250°C plasma clean. The high temperature enables efficient desorption of native oxide, but at the expense of forming elemental antimony, which increases the interface trap density. By optimising the H2 plasma surface clean temperature for a 3.5 nm-thick HfO2 gate dielectric, we realise the thinnest capacitance equivalent thickness, of around 1.2 nm, with the lowest mid-gap density of interface traps (see Figure 4 (a) and (b)).  This enables efficient movement of the Fermi level between the valence band and the mid-gap, but sluggish movement away from mid-gap (see Figure 4 (c), which illustrates this behaviour with normalized conductance maps). 


Figure 4. (a) Optimized capacitance-voltage characteristics of p-type GaAs0.35Sb0.65 MOSCAPs with a 3.5 nm HfO2 gate dielectric using a H2 plasma surface clean; (b) interface trap density extraction using Terman method. Gate leakage is shown in the inset; (c) Normalized parallel conductance plot with dotted line trace showing movement of the conductance peak maximum. Efficient Fermi level movement is obtained till mid-bandgap. Mid-gap interface trap density pins the Fermi level movement at low frequency.

The n-type FET faces similar challenges to its p-type sibling, with the interface between a ZrO2 gate dielectric and an In0.65Ga0.35As channel marked by the presence of dangling bonds, As-As bonds, arsenide-oxides and anti-site defects. To eradicate arsenide-oxides and passivate the interface, we combine an ex-situ buffered oxide etch clean with an in-situ N2 plasma/TMA [trimethylaluminum] cyclic treatment. 

Surfaces can be damaged with over exposure to the plasma, so we limited the number of cycles to nine. Taking this approach and using a 4 nm-thick ZrO2 high-K dielectric, we produce devices with a capacitance equivalent thickness of 1.1 nm and a low mid-gap density of interface traps (see Figures 5 (a) and (b)). Measurements of the conductance peak indicate efficient Fermi-level movement with gate voltage (see Figure 5 (c)).



Figure 5. (a) Optimized capacitance-voltage characteristics of n-type In0.53Ga0.47As MOSCAPs with 4nm ZrO2 gate dielectric using N2 plasma/TMA clean; (b) interface trap density extraction using the Terman method. Gate leakage for both the 3 nm and 4 nm ZrO2 dielectrics is shown in the inset; (c) Normalized parallel conductance plots for 4 nm ZrO2. Dotted line trace shows efficient Fermi level movement throughout the band gap.

We have measured the room-temperature transfer and output characteristics of our n-type and p-type hetero-junction tunnel FETs (see Figure 6). The p-type devices deliver an on-current of 30 ÂµA/µm and produce an on-off current ratio of 105. When these transistors are cooled by liquid nitrogen, they exhibit negative differential resistance and saturation, due to the suppression of a response from the mid-gap interface traps. With n-type devices, the on-current is 275 ÂµA/ Âµm and the ratio of on-to-off current is 3 x 105.


Figure 6. DC transfer and output characteristics of (a-c) a p-type hetero-junction tunnel FET and (d-f) an n-type hetero-junction tunnel FET. All measurements are at T=300K, except the additional T=77K data in (c) and (f). Negative differential resistance is visible in the p-type transistor's output characteristics at T=77K, due to the suppression of trap response. NS denotes the source doping concentration in the device.

One major downside of the slow response time associated with the mid-gap interface traps is that it causes the DC switching slope for both types of FET to exceed 60 mV/decade at room temperature. However, it is possible to suppress the impact of mid-gap interface traps on the sub-threshold slope by sweeping the gate voltage at a rate that is faster than the trap response time. 

We took this approach, evaluating the switching slope with an input gate voltage ramp rise time that varied from 10 µs to 300 ns. Using these conditions, switching characteristics improved, with room-temperature values for the n-type and p-type FETs of 55 mV/decade and 115 mV/decade, respectively. These switching slopes and high currents highlight the importance of employing high-quality, scaled gate dielectrics and tunnel barriers in the arsenide-antimonide system.



Figure 7. Fast IDS-VGS measurements reveal improved switching characteristics in p- and n-hetero-junction tunnel FETs. All measurements at 300K


To put our results in context, we have benchmarked our devices against published results (see Figure 8). This comparison includes hetero-junction tunnel FETs made with silicon/SOI/SiGe materials that deliver steep switching, but not in conjunction with a high current. Our antimonide-based n-type transistors deliver superior performance, and when partnered with our p-type arsenide-channel devices, demonstrate the potential of III-V complimentary tunnel FET logic. 

We will now build on our work. We have already accomplished the first demonstration of an all III-V material system based on complimentary hetero-junction FETs that combines a low operating voltage with a record on-current and switching performance. Our goals for the future include an expansion of the steep switching range over multiple decades of drain current without compromising the on-current. We know that cutting contributions to parasitic leakage and engineering high-quality interfaces hold the key to realising high-performance hetero-junction tunnel FETs with a steep switching slope that can serve energy-efficient logic.


Figure 8. Benchmark of silicon and III-V TFET. VON (VMIN) corresponds to the gate voltage at ION (IMIN). |VON| is limited to 1.5 V from |VMIN|




AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.

REGISTER FOR FREE

VIEW SESSIONS

Info
×
Search the news archive

To close this popup you can press escape or click the close icon.
×
Logo
×
Register - Step 1

You may choose to subscribe to the Compound Semiconductor Magazine, the Compound Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
 
X
Info
X
Info
{taasPodcastNotification}
Live Event