Integrating MicroLEDs With Advanced CMOS
Bonding 300 mm GaN-on-silicon LED wafers to CMOS backplanes of the same size offers the best approach for producing displays that have a microLED pitch of just a few microns.
BY Soeren Steudel FROM MICLEDI Microdisplays
For the last five years or so microLED manufacturing has been a very hottopic within the display industry. It's been high on the agenda at leadingdisplay events, such as Display Week, with the focus on flat panelmanufacturing of various displays, ranging in size from smart watches to mobilephones and TVs. For this technology, efforts at scaling manufacture arethwarted by challenges associated with mass transfer of the microLED, as wellas the repair of defective die.
A new set of issues are facedwhen considering microLEDs for microdisplay applications, likeaugmented-reality (AR) glasses. One approach to making a microLED-based displaymodule for that type of application involves uniting microLEDs and CMOSbackplane ASICs, which control and drive the microLEDs. This approacheliminates issues associated with mass transfer, but comes up against adifferent set of obstacles. Consider the primary application on the horizon forthis technology, AR glasses: there's a need for a brightness exceeding1 Mnits, pixel pitches below 3 mm, a resolution of up to 2K andbeyond, ultra-low power consumption and acceptable cost, all in a light-weightmodule.
As of today, none of thesespecifications are being met by existing microdisplay manufacturing methods.But progress is underway. The chipmaker JBD of Shanghai, China, has introducedseveral impressive prototypes and is delivering modest volumes. However,high-volume manufacturing is elusive. Meanwhile, our company, MICLEDIMicrodisplays of Leuven, Belgium, is making good strides on addressing issuesthat limit the brightness and resolution of microLED displays. To this end, weare developing an approach that's needed to deliver high-volume, low-costmanufacturing. Read on to discover the details of the challenges we face andour compelling solutions.
Figure 1. Light-outcoupling in a planar microLED with (a)small pixel versus a (b) tight-pitched array.
Brightness and efficiency
One weakness of AR glasses istheir very substantial optical losses. The extent of this is governed by the implementation, but often less than just 1 percent of the photons emitted by the display arrive in the eye. Due to thesestaggering losses, displays have to generate up to 10 million nits of whitelight to support outdoor usage with high-transparency glasses.
A comparable microOLED display,which is a rival technology to the microLED display, can achieve in the bestcase 20 knits for green, even though the efficiency number for OLED willbe better than for microLED. A summary of the state-of-the-art by YoleIntelligence, the French market analyst, in 2019, showed efficiency numbers forOLED (RGB - 22 percent, 22 percent, 7 percent), versus the 5 mmmicroLED (RGB - 7 percent, 15 percent, 25 percent). Note that these figures are farbelow the values for the internal quantum efficiency of the GaN LED, which has atypical value of 85 percent in the blue, 60 percent in the green and less than30 percent in the red.
Efficiency losses at scaleddimension are mostly due to optical outcoupling and, to a lesser extent,electrical losses due to defects at the mesa sidewalls, leading to a highamount of non-radiative recombination and an increased leakage current. Thelight-outcoupling in a planar LED is limited by the angle of internalreflection from the high index compound semiconductor material into air. Thisautomatically means that for a GaN LED, less than 10 percent of the lightcan be extracted with a perfect backside mirror, neglecting interferenceeffects. For larger LEDs with dimensions greater than 100 mm,surface texturing is applied with a very good backside mirror. This enablesevery photon to have multiple chances of escaping under different angles,leading to a theoretical light extraction efficiency of 75 percent.Surface texturing is not a solution for microLEDs with dimensions below 5 mmsince there is no space for the photon to undergo multiple reflections.
Figure 2. ((left) Field-of-view (FOV) plotted as a functionof pixel number for different angular resolutions (Mpixel refers to 1 pixelwith a red-green-blue sub-pixel with a display ratio 1:1); (right) Die size fordifferent sub-pixel pitches (assuming an advanced node CMOS (<45nm) with aframebuffer and a display ratio 16:9).
It's also worth noting that theefficiencies provided by Yole are very optimistic, and only apply to individualLEDs spaced very far apart. This is illustrated in Figure 1, which considersdifferent spacing scenarios. In microLEDs, the direct emission through thetransparent front-side contact is very low, typically below 10 percent - butextraction can be boosted by adding a sidewall mirror that extracts lightbeyond the angle of internal reflection. However, when packing microLEDs closertogether to ensure a higher pitch, any type of sidewall mirror is lesseffective. Due to this impediment, the external quantum efficiency of microLEDsin very small displays is expected to be limited to no more than 8 percent,unless there is a shift to a directional emitter architecture.
So, given these low values formicroLED efficiency, these devices are still seen as a viable alternative to OLEDs, because they have a vastlysuperior current handling capability. By being able to sustain a currentdensity that is more than a thousand times higher than an OLED canhandle, these GaN-based devices can deliverthe target brightness.
Figure 3. Die yield versus field-of-view (FOV) for differentsub-pixel pitches. (left) assumes RGB pixel-by-pixel; (right) assumes RGBdie-by-die.
Display size and resolution
Twoquestions for any display based on the microLED are: What is its required size?And what resolution is appropriate? To answer them, it's imperative to considerthe capabilities of the human eye. In both the green and blue spectral domain,the human eye has an angular resolution of 60 pixels per degree. We noted thisfigure when considering the targeted field-of-view for AR glasses. As one wouldexpect, the number of pixels in a display must increase when increasing thefield of view, or the angular resolution (see Figure 2, left). In some currentcommercial headsets, where the system supports a full high-definition display,there is a limited field-of-view of 50°. One benefit of moving from 5 mm to 1 mm microLEDs is that they can offer a larger field-of-view from the samedisplay size (see Figure 2, right).
While this level ofminiaturisation is appealing, it is far from easy to realise with routinesuccess. Even the manufacture of a full high-definition display with 5 mmpitch approaches the limits of the reticule size of the exposure tool.Operating near this limit impacts manufacturability and yield.
We have calculated the impact ofyield for different pitches. According to our manufacturing yield model (seeFigure 3, left) - that assumes red, green and blue microLEDs co-integratedside-by-side - even when the target resolution is reduced to only 40 pixels per degree, a pitch of less than 3 mm is needed to exceed a50 percent yield.
It is possible to significantlyrelax these conditions by manufacturing three different colours of emitterindependently, before bringing them together with an optical combiner (seeFigure 3, right). This gets far closer to the yield model of an incumbentcolour display technology, known as the sequential liquid-crystal-on-silicondisplay.
Figure 4. Overview of microLED-on-CMOS integration schemes.
Manufacturability
Over the last ten years severalgroups have scaled the dimensions of the microLED below 1 mm.However, for these researchers, it is often only an afterthought to considerthe integration of the LED pixel with the CMOS driver circuit, commonly knownas the ‘backplane' IC.
A number of approaches may betaken to realise this integration (options are summarised in Figure 4).One is die-to-wafer transfer, accomplished by either transferring and placingpixels one at a time to create an array ofred, green and blue emitters, or by bonding the full array as an individualchiplet. Both these die-to-wafer transfers employ indium bumps, a technologythat's been used in the mass production of infrared imagers for more than 20years. Another strength of die-to-wafer transfer is that it allows the CMOSbackplane to be made in a standard CMOS fab, and the front-plane diode array ina compound semiconductor fab - with each fab tailored to the particular wafersize and using dedicated tool sets. With this approach, production scales wellto a pitch of 10 mm, before significant yield losses arise. There are also otherdie-to-wafer approaches with other types of micro-bumps, as well as hybridbonding.
For military and spaceapplications, ultraviolet and infrared imagers have been produced with pitchesas low as 4 mm using die-to-wafer bonding. However, yield is very low - it'sunacceptable for the display industry. So, for microLED displays, a fullwafer-to-wafer approach is needed to go below a 10 µm pitch and combine the LED with the backplane. If wafer-to-wafer bondingis to be employed alongside a sequential 3D approach, the LED array wafer andthe CMOS wafer must be the same size. That presents a problem: as microLEDsrequire more complex driving and compensation schemes compared with OLEDdisplays, such as the inclusion of a framebuffer, the accompanying siliconcircuitry must be made on 300 mm wafers, using advanced nodes that are wellbelow 45 nm. As no 300 mm compound semiconductor epiwafers are produced involume, efforts are currently directed at resizing (coring) larger CMOS wafersto 100 mm or 150 mm in diameter, resulting in costly wafer area loss. Progresswith hybrid bonding is also hampered by the need for extreme surface planarity,as well as a very low wafer bow and generally low stress. All theserequirements are challenging to fulfil with nearly every compound semiconductorstack deposited by heteroepitaxy.
Figure 5. Manufacturing flow from 300 mm compound semiconductor reconstitution to hybrid bonding of a diode array with an advanced node CMOS.
What's encouraging is thatproduction processes to stack silicon wafers arealready in use, combining sequential 3D structures with through-substrate viasand wafer-to-wafer hybrid bonding. The latter is commonly employed forproducing backside-illuminated imagers with a pitch down to 3 mm,and is used in R&D departments to unite 300 mm wafers at a pitch down to 1 mmwith overlays less than 200 nm.
Display integration
Our company, a spin-out of imecthat launched in 2019, is on a mission to solve the manufacturability and yieldissues outlined above. While developing our display technology, the decisionsthat we have taken have adhered to the three following premises: ourintegration flow is developed on 300 mm production equipment, so that it can betransferred to a CMOS foundry; the materials we select are as compatible aspossible with the contamination and waste management protocols of advanced CMOSfabs - so that means no silver, gold or GaAs; and that, as much as possible,established process steps and modules are adopted that have delivered highyields when manufacturing other products.
With these requirements at theforefront of our mind, we have developed an LED integration process that isvery similar to that employed for making 3D backside-illuminated imagers.However, in our case we replace the silicon-photodiode wafers with thatpopulated by GaN diodes (see Figure 5). We have overcome the limitations of thestarting GaN material, such as its small size, significant stress and bow, andits high particle density, by sourcing best-in-class commercial epiwafers,screened from multiple vendors. Epi-dice are cut to the size of the finaldisplay, such as 4 mm by 6 mm for a full high-definition, prior toredistribution across a
blank silicon wafer. Followingremoval and planarization of the epi-growth substrate and the buffer layer, weproduce a stress-free 300 mm-diameter structure with known good epi-diepre-selected, so that only a 1.5 mm-thick GaN stack remains,featuring an active region sandwiched between doped layers (see Figure 6 (a)).From a wafer-handling perspective, this reconstituted wafer behaves like asilicon-wafer.
Figure 6. Images of a 300 mm LED wafer (a) after GaN reconstitution; (b) after a full wafer-to-wafer integration scheme. (c) packaged die. (d) a 480 x 320 passive array with 9150 ppi.
Processing creates LEDs with a 3 mmpitch on a 300 mm wafer. Subsequent wafer-to-wafer hybrid bonding unites thiswafer to a 300 mm CMOS backplane ASIC wafer with an alignment accuracy tighterthan 250 nm. For our initial process development, device characterization and sampling, we used a silicon waferwith just a few metal layers, limiting operation to passive control of thematrix arrays (see Figure 6 (d) for wafer-level testing of a passive array of480 pixels by 320 pixels; Figure 6 (c) for an image of packaged die; andFigure 6 (e) for a microscopic image of the array with a 3 mmpitch and a 2 mm mesa). Our next step is to replace these passive arrays withan actual ASIC.
Using this integration scheme, wehave realised a record aperture of up to 65 percent, with a mesa of 2.5 mmin a 3 mm hexagon-pitch configuration. This large aperture is atremendous attribute, essential to achieving high brightness. The firstblue-emitting wafers coming off the line have a brightness of 600,000 nits at 5V. For these emitters, external quantum efficiency is more than 2 percent.
Our current approach is to drawtogether the output of red, green and blue die with an optical combiner. One implicationof this methodology is that we have to use the same process flow for all threeforms of die. As expected, it is the red LED that is providing the biggestchallenge. Work is ongoing to improve the efficiency and the colour point. Thefirst short-loop sample of a red source, formed from a 200 mm GaN-on-siliconepiwafer, can be seen in Figure 7.
Figure 7. Electroluminescence image of a red GaN-on-silicon linear array with a 7.5 µm mesa.
Improving the wafer-level opticsoffers another avenue for raising performance. It should be possible to enhancebrightness by a factor of two-to-four by enhancing light-outcoupling within theapex angle that is useful for waveguide integration - and suppressing lightemission that is outside this angle. In a relatively short time wehave demonstrated that for pitches of 5 mm and below, there ismuch merit in turning to a monolithic approach that involves bonding a 300 mmmicroLED wafer to a CMOS backplane wafer. Working with our partners at imec, wehave addressed the challenges associated with the process, and we are now startingto transfer our technology to our foundry partner.
£ The authors would liketo acknowledge the collaboration with the imec 300 mm pilot line and the imec 3D integration department.
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