SiC: A solution for photonics?
By combining controlled thickness with low defect density and industrial compatibility, Smart-Cut technology is creating high-quality SiC-on-insulator substrates that are opening the door to practical photonic integrated circuits.
BY STÉPHANIE HUET FROM CEA-LETI
While SiC is best known as a material for power electronics, that’s not its only application. This wide bandgap material is rapidly emerging as a compelling platform for next-generation photonic technologies, with applications ranging from non-linear optics to quantum systems. SiC provides a broad transparency window, strong optical non-linearities, and remarkable thermal robustness – that’s a unique combination of properties that few materials match.
Yet despite these advantages, SiC photonics has failed to make the leap from lab to fab. That’s not due to a lack of performance, but the absence of suitable substrates. It is challenging to produce high-quality SiC-on-insulator wafers, essential for guiding light efficiently, at scale and reasonable cost.
Overcoming this limitation is a critical challenge. Without a viable substrate platform, it’s impossible to transition even the most promising device concepts into real-world technologies.
Rising platform
The appeal of SiC lies in its unique and wonderful set of attributes. Thanks to a bandgap that ranges from about 2.4 eV to 3.2 eV, this material supports operation from the visible to the mid-infrared. At the same time, it exhibits both second- and third-order optical non-linearities, enabling functions such as frequency conversion and high-speed modulation.
In practical terms, this means that SiC can support applications that are difficult to implement with silicon or SiN. There are opportunities in high-power photonic circuits, non-linear optical devices, and quantum systems based on optically active defects.
Key to exploiting these properties is tight optical confinement. In many ways, this mirrors the challenge encountered in optical fibres, where light is guided within a high-refractive-index core that’s surrounded by lower-index materials. A comparable principle applies to SiC photonic devices.
From fibre to chip: light confinement in an optical fibre (left) and in a SiC-on-insulator waveguide (centre), where a 500 nm SiC layer on a 3.5 µm oxide enables strong confinement at 1550 nm; scanning electron microscopy cross section image (right) shows the fabricated structure.
However, instead of a cylindrical fibre, the structure is formed as a planar waveguide on a chip. In this case, a very thin layer of SiC acts as the region carrying light, with the surrounding materials ensuring confinement.
Many of the devices made from SiC are designed to operate at 1550 nm – that’s the standard wavelength for optical communications. At this wavelength, the SiC layer must be thin, typically around 500 nm. Below this layer is a buried silicon dioxide layer, typically about 3.5 µm-thick, that’s either exposed to air or covered by another dielectric material.
The resulting stack provides a strong refractive-index contrast, ensuring that light is tightly confined within the SiC layer as it propagates through the device. Unlike optical fibres, which are flexible and guide light over kilometres, these waveguides are rigid structures fabricated on a chip, with light manipulated over much shorter distances.
With these optical SiC-based chips, a high level of control is critical. Even small variations in thickness or interface quality increase optical losses and degrade performance.
Critical bottleneck
Developing SiC-on-insulator substrates has been far more challenging than initially anticipated. Unlike silicon photonics, which benefits from decades of industrial infrastructure built around silicon-on-insulator wafers, SiC photonics lacks a mature, widely available substrate technology.
Early demonstrations employed bespoke substrates, fabricated using bonding and thinning techniques. While excellent material quality is possible, there are significant downsides, including poor thickness control, with variations reaching the micrometre scale, and an inherently wasteful process – much of the original material is removed. Turning to amorphous deposition improves scalability, but at the expense of optical performance. The absence of crystalline order limits non-linear effects and increases propagation losses, making these substrates less suitable for demanding photonic applications.
Smart Cut process for SiC-on-insulator substrates, enabling the transfer of a thin SiC layer and its optimisation through annealing and polishing for photonic applications.
Due to these issues, developers of SiC photonic technologies are caught between high-performance, impractical solutions, and scalable, lower-quality alternatives. Bridging this gap is essential for industrialisation of SiC photonics.
Top view of a 150 mm SiC-on-insulator wafer demonstrating scalable fabrication of the platform.
Smart Cut edge
One promising route for overcoming these limitations involves turning to ion-cutting techniques, and in particular the Smart Cut process. Originally developed for fabricating silicon-on-insulator wafers, this technology is now producing thin, uniform layers with high reproducibility on an industrial scale.
When Smart Cut technology is applied to SiC, a thin crystalline layer of this wide bandgap material is transferred from a donor wafer onto a handle substrate, with a SiO2 layer in between. This oxide layer provides the refractive-index contrast needed to confine light within the SiC layer, while the transfer process preserves the crystalline properties required for photonic devices.
A key strength of this method is its efficiency. Unlike bonding and thinning, the donor wafer can be reused, slashing material consumption and cost. And it’s possible to control the thickness of the transferred layer with high precision, enabling the fabrication of waveguides with optimised optical properties.
The big challenge is to adapt Smart Cut to SiC – and that’s not straightforward. The issue is that the quality of the transferred layer can be degraded during ion implantation, bonding, and high-temperature annealing. Preventing this from happening is crucial when attempting to produce a viable photonic platform.
Process control
To address these challenges, our team at CEA-Leti has developed an optimised fabrication process for SiC-on-insulator substrates that’s based on Smart Cut technology. Our approach focuses on three key matters: ion implantation conditions, thermal budget, and surface finishing.
Our process begins with the preparation of donor and handle wafers. Both are coated with a silicon dioxide layer. A fracture plane is then defined within the donor substrate with hydrogen ion implantation. As this step may introduce defects that diminish optical performance, we carefully optimised implantation conditions to minimise crystal damage while preserving efficient layer transfer. After bonding the two wafers through their oxide layers, we use thermal annealing to induce the transfer of a thin SiC layer onto the handle substrate.
A critical parameter for our process is the thermal budget. Annealing temperatures between 1200 °C and 1400 °C play a central role in restoring the crystalline quality of the transferred layer. Annealing at 1200 °C leads to a significant recovery of the crystal structure, and when we increase the temperature towards 1400°C, material quality improves, coming close to that of bulk substrates.
It should be noted that we realise high material quality at temperatures compatible with silicon-based substrates. This opens the possibility to integrate SiC photonics with conventional microelectronics platforms.
Crystal quality
The effectiveness of our optimised process is reflected in the structural and morphological properties of the resulting substrates. Across 150 mm wafers, we transfer a SiC layer with a thickness close to 500 nm, chosen as it corresponds to the optimal value for a waveguide operating at telecom wavelengths.
For SiC photonic applications, surface quality is equally critical. Immediately after layer transfer, surface roughness can be a concern, as it’s on the order of several nanometres. But this is reduced dramatically after chemical-mechanical polishing, to around just 0.15-0.2 nm. These ultra-smooth surfaces are essential for minimising optical scattering losses in waveguides.
At the crystalline level, advanced characterisation techniques reveal a clear improvement in material quality after annealing. According to X-ray diffraction measurements, there’s a reduction in peak broadening, indicating a decrease in lattice disorder. Raman spectroscopy reveals a similar story, with annealing enhancing crystalline coherence.
Thickness uniformity map of the transferred SiC layer across the wafer (left), showing a 3σ non-uniformity of 5.7 percent. Atomic force microscopy scans (right) compare surface roughness before and after chemical-mechanical polishing, demonstrating significant surface improvement.
A more direct view of our material is provided with transmission electron microscopy. Images reveal that the transferred layer features well-defined lattice structures and clean interfaces. There are no detectable defects at the SiC/oxide boundaries.
Based on these findings, we can conclude that the combination of implantation, annealing, and polishing produces a high-quality crystalline film that’s suitable for photonic applications.
Defect reduction
As well as ensuring sufficient structural quality, the control of defects within a material enables low optical losses. Even when the crystal lattice appears largely recovered, it’s possible that residual defects interact with light and degrade device performance.
Helping determine if that is the case are photoluminescence measurements, which are highly sensitive to the presence of defect-related states. Using this optical technique, we uncovered broad defect-related emission bands associated with implantation-induced damage and defect complexes within the transferred layer.
When we optimise our implantation process, there’s a clear reduction in these unwanted signatures, which were more prevalent in our previous generation of substrates. We find that as the material recovers, defect-related luminescence decreases, indicating a lower density of optically active defects. Cathodoluminescence measurements support this observation, showing a significant reduction in deep-level defect emissions.
Drawing on these insights, we have established that improving crystalline quality is only part of the solution. It’s equally important to reduce residual defect populations, as they ultimately determine the optical quality of the material and its suitability for low-loss photonic devices.
Fortunately, we have demonstrated that through careful control of implantation and annealing conditions, we can significantly improve the optical quality of SiC-on-insulator substrates.
Device impact
While material characterisation provides important insight, the ultimate test for any photonic platform is device performance. In this context, our improvements have direct implications for the fabrication of waveguides and other integrated components.
It is expected that the combination of precise thickness control, low surface roughness, and high crystalline quality trims propagation losses and enhances device efficiency. Smoother interfaces and fewer defects should reduce scattering and absorption, both of which are critical for high-performance photonic circuits.
Cross-sectional transmission electron microscopy (TEM) image of the optimised SiC-on-insulator structure after 1200 °C annealing (left). High-resolution TEM images and corresponding selected-area electron diffraction patterns (right) reveal a high crystalline quality within the transferred SiC layer.
Moreover, by producing uniform substrates at the wafer scale, we are opening the door to more complex and densely integrated devices. This could be a game-changer for applications such as quantum photonics, where numerous components must operate coherently on a single chip.
Although our detailed device measurements are ongoing, and we cannot disclose any details at this stage, our material properties are providing a strong foundation for the development of competitive
SiC photonic technologies.
Photoluminescence spectra obtained at 405 nm excitation for SiCOI substrates post-annealed at (a) 1200 °C, (b) 1300 °C and (c) 1400 °C fabricated with previous process and new process.
Future devices
Producing high-quality SiC-on-insulator substrates is not an objective in itself. The value of these structures lies in the photonic devices that can be built on top of them.
The most straightforward applications are low-loss waveguides, ring resonators and interferometers, as these devices are the building blocks of photonic integrated circuits. These devices are used to route, filter and manipulate light, in much the same way that transistors control electrical signals in conventional electronics.
When we look beyond passive devices, we have opportunities with SiC that are difficult to accomplish with silicon alone. The electro-optic and non-linear optical properties of SiC can be exploited to realise functions such as high-speed modulation, wavelength conversion and frequency comb generation – all are attracting growing interest for telecommunications and optical sensing.
Another promising area is quantum photonics. SiC can host optically active colour centres that emit single photons and act as quantum bits. Combining these quantum functionalities with wafer-scale photonic integration could enable compact chips for quantum communication and quantum sensing.
Due to this combination of functions, SiC-on-insulator is a promising platform for a wide range of integrated photonic devices.
Future scale
Beyond immediate performance gains, the broader significance of our work lies in its industrial potential. By leveraging a mature, scalable process such as Smart Cut, SiC photonics can be aligned with existing semiconductor manufacturing infrastructures.
A highlight of our work is that it shows that Smart Cut technology is compatible with different handle substrates. While the use of SiC handles enables high-temperature processing and optimal material matching, transferring the SiC layer onto silicon substrates offers additional advantages. In particular, this transfer facilitates integration with conventional microelectronics, and reduces overall system cost.
Our possible plans for further development include using polycrystalline SiC substrates to create fully SiC-based structures. In parallel, we may scale the process to larger wafer sizes, such as 200 mm, as this will be essential for realising the economies of scale for commercial deployment.
More broadly, our approach offers a way to reconcile three key, often conflicting requirements: high material quality, process scalability, and cost efficiency. Some success on all three fronts is critical for moving SiC photonics from the laboratory to real-world applications.
In short, rather than simply improving a fabrication process, our work opens the door to the industrialisation of SiC photonics. By combining Smart Cut technology with optimised implantation and annealing, we have provided a pathway to realising high material quality while maintaining scalability and cost efficiency.
As SiC photonics progresses towards practical applications, the availability of targeted, high-quality substrates will play a decisive role. Thanks to our advances, SiC is no longer just a promising material – it is now on the cusp of becoming a realistic platform for next-generation photonic integrated circuits.
Further reading
S. Huet et al. “Demonstration of SiC-on-Insulator Substrate with Smart Cut Technology for Photonic Applications” Materials Science Forum 1124 67 (2024)
S. Huet et al. “Enabling SiC Photonic Platforms with Smart Cut™: Material Quality and Process Optimization of SiCOI Substrates” ICSCRM 2025
