The troiumvirate for tomorrow's wireless

Next-generation wireless communication systems will benefit from heterogeneous monolithic integration of InGaAs HEMTs and GaN HEMTs on silicon CMOS chips.

BY JAEYONG JEONG, CHAN JIK LEE, YOON-JE SUH, NAHYUN RHEEM, BONG HO KIM, JOON PYO KIM, JUHYUK PARK AND SANGHYEON KIM FROM KAIST

Wireless communication systems are the neural network of modern infrastructure, supporting a vast array of interconnected services. It’s vital that they provide reliable connectivity to support the rapid expansion in autonomous transportation and advanced AI platforms. Both these sophisticated technologies generate and process immense volumes of data in real time, and require unprecedented transmission speeds to function effectively.

To address these demanding requirements, researchers must explore opportunities to expand physical channel capacity through fundamental hardware innovation. At the Korea Advanced Institute of Science & Technology (KAIST), our team is taking on this challenge, through the integration of III-V and III-N transistors onto silicon substrates. This triumvirate is pushing the boundaries of high-performance, RF blocks.

Our efforts at expanding channel capacity are drawing on two primary physical pillars: the widening of the available bandwidth, and an increase in the signal-to-noise ratio. A wider bandwidth necessitates a transition to a higher frequency spectrum, where more spectral resources are currently underutilised. This move must go hand-in-hand with maintaining a high signal-to-noise ratio at these frequencies – and that requires exceptional performance from both the transmitter and the receiver ends of the system. Power amplifiers must deliver high output at the source, while low-noise amplifiers must preserve signal integrity at the destination. To excel on these two fronts, both components must be seamlessly coupled with high-gain antennas, to ensure the efficient radiation and reception of signals across the environment.

Breaking limits
It is the physical properties of semiconductor materials that dictate the ultimate performance limits of high-frequency communication systems. Within the portfolio of compound semiconductor materials, InGaAs and GaN are the premier candidates for low-noise and high-power applications, respectively. InGaAs devices are renowned for their remarkable low-noise characteristics in the 100 GHz range, making them ideal for sensitive receivers; and GaN transistors offer exceptionally high-power saturation levels within the same frequency bands for transmission. We utilised these two materials during our development of a robust RF front-end that leverages a wide bandwidth while maintaining a superior signal-to-noise ratio.

Our technology draws on significant breakthroughs in antenna design and spatial multiplexing.

Early wireless systems relied on basic single-input, single-output structures, which tended to limit capacity, and were often hampered by interference. They have been superseded by multiple-input, multiple-output (MIMO) configurations that increase data throughput in crowded environments. However, as operating frequencies increase and move towards the millimetre-wave and sub-terahertz regimes, traditional architectures face severe physical constraints.

Due to this, phased-array antenna technology, based on massive MIMO systems, is emerging as the leading solution for next-generation wireless hardware. Utilising advanced beamforming, these systems concentrate electromagnetic energy into precise spatial directions for targeted communication. Spatial focusing is a game changer, dramatically increasing the communication range and its capacity by cutting energy waste and minimising interference with other users. Implementing these arrays requires the dense integration of many individual antenna elements with respective control circuits.

Unfortunately, dense integration is far from trivial. One major issue is that conventional 2D packaging technologies fail to fulfil the tight integration requirements demanded by modern phased-array antenna systems. Using a side-by-side layout, it is physically difficult to integrate an InGaAs Low Noise Amplifier (LNA), a GaN Power Amplifier (PA), and silicon-based control chips. This challenge arises because as the operating frequency increases, the physical size of the antenna elements tracks those changes in signal wavelength – while the supporting control electronics and RF components scale far more slowly. This mismatch in component sizes leads to long interconnects, which introduce parasitic losses and degrade signal performance at high frequencies.

Figure 1. An illustration of the essential components of a next-generation radio frequency communication system. KAIST selects InGaAs and GaN for the front end, due to their superior noise and power performance at 100 GHz. Antenna technology has evolved, from simple structures to massive multiple-input multiple-output (MIMO) phased arrays to meet high-capacity demands. This integrated strategy is critical for supporting the extreme data rates of future wireless standards.

Offering a powerful, compelling alternative is vertical 3D integration technology. By allowing the stacking of different semiconductor layers directly on top of each other, this form of integration maximises spatial efficiency and shortens the signal paths between active devices and antenna.

Figure 2. The scaling mismatch between antenna elements and supporting integrated circuits creates a significant architectural challenge as operating frequencies increase. While antenna size shrinks rapidly according to wavelength, the circuitry footprint remains relatively large, leading to a physical size gap. Vertical 3D integration resolves this bottleneck by stacking functional layers directly beneath the antenna array. This approach ensures a compact, efficient footprint for high-frequency phased-array systems.

Vertical integration: Pros and cons
One great strength of vertical stacking is that it allows the creation of heterogeneous systems where each material is utilised for its specific strengths. This is realised without compromising the overall footprint.

Figure 3. A comparison of 3D integration pathways highlights the optimal balance between process complexity and manufacturing yield. Utilising monolithic integration to build a pre-verified RF block before bonding ensures a high yield through the known good die approach. Other sequential methods are less effective, due to increased bonding steps or significant yield loss. A modular manufacturing flow provides the most advantageous strategy for ensuring overall system reliability.

Using this approach, we handle control logic and complex signal processing with cost-effective silicon CMOS processes. Meanwhile, high-performance RF functions are delegated to specialised compound semiconductor layers, bonded directly to the silicon base.

Figure 4. 3D integration process for an RF block on a silicon CMOS chip.

Adopting this strategy allows us to use expensive compound materials only where they are strictly necessary for electrical performance. This platform opens the door to fully integrated antenna modules that house all necessary components in a single compact package.

Motivated by these architectural advantages, we overcome formidable technical hurdles to combining diverse compound semiconductors on a silicon platform. It is extremely difficult to grow compound semiconductor layers directly on silicon, due to the significant mismatch in crystal lattice constants. There are also differences in the coefficients of thermal expansion of these materials, leading to mechanical stress and structural defects during fabrication.

Yet another obstacle is the high temperatures that are required for manufacturing GaN devices, which threaten to damage pre-existing structures on the chip. To address all these concerns, we introduced an innovative fabrication flow that stabilises these disparate materials without sacrificing their individual device characteristics.

With our fabrication flow, we realise a heterogeneous 3D stacking architecture that combines GaN HEMTs with InGaAs HEMTs on a silicon CMOS chip. This process begins with the fabrication of GaN HEMTs, and is followed by the integration of InGaAs layers, which provide low-noise functionality. We combine these two RF blocks into a single chip unit, which is transferred to the silicon control circuitry.

To combine different material technologies, we utilise a sophisticated die-to-wafer bonding technique that ensures a stable mechanical and electrical connection between the layers. With this methodology, we minimise the number of interlayer vias required, and significantly improve the overall integrity of high-frequency signals.

When forming our heterogeneous structures, we begin by producing an RF block. This involves the integration of InGaAs devices onto GaN devices via monolithic 3D integration. We then integrate this completed RF block onto the silicon CMOS chip using a secondary vertical process.

Our approach avoids integrating individual components sequentially onto the silicon chip. If we adopted that approach, it would be impossible to verify the operation of the RF block before bonding. By avoiding this limitation regarding known good die, we do not suffer from an inevitable reduction in the overall manufacturing yield. Additionally, we reject stacking GaN devices onto InGaAs devices, as this would involve a redundant and costly bonding step.

Figure 5. KAIST’s successful vertical integration of the RF block onto a silicon CMOS chip. A 3D integrated InGaAs LNA and GaN HEMT maintain superior RF performance.

Process design strategy
The fabrication sequence that we have devised, involving three primary stages, starts with the standard manufacture of GaN HEMTs. Their production includes conventional high-temperature annealing to form source and drain ohmic contacts. For the subsequent monolithic integration of the InGaAs layer, we employ an inverted transistor structure. Our specific design choice ensures superior alignment. The resulting composite block provides a high-performance engine for the transmit and receive paths of the communication system.

We use a two-stage bonding process to transfer our dual material RF block onto our silicon CMOS chip. We begin by bonding the block to a temporary carrier wafer in an inverted orientation, to allow removal of the silicon substrate of the GaN HEMT. After removing this substrate, the RF block is permanently attached to the top of the silicon control chip.

For the bonding stages, we made several critical engineering choices to ensure the thermal and mechanical stability of the final device. To facilitate efficient heat dissipation away from the GaN PA, we implemented a metal bonding interface. This high-power device generates significant heat during operation, so thermal management is critical to prevent thermal degradation of the surrounding circuits.

The entire bonding sequence proceeds below 150 ˚C to protect the integrity of the pre-fabricated transistors. This low-temperature budget maintains delicate doping profiles, as well as the metal interfaces of the underlying silicon and compound semiconductor devices.

With our delicate and considered approach, the structural integrity and electrical characteristics of our InGaAs and GaN transistors remain stable throughout the integration process. According to post-integration testing, our HEMTs maintain their high-frequency capabilities without significant performance loss. The 3D integrated InGaAs HEMTs have a cut-off frequency of 320 GHz and a maximum oscillation frequency of 293 GHz, and the corresponding figures for GaN HEMTs are 108 GHz and 115 GHz, respectively. These results confirm that our vertical integration approach is compatible with the most demanding requirements of the sub-terahertz frequency spectrum.

Future communication vistas

Our research establishes a viable pathway for vertical integration of high-performance compound semiconductors. By maximising the strengths of different material systems, we have created a platform that combines high-power and low-noise capabilities in a compact form factor.

In addition to this asset, there’s a drastic reduction in the physical footprint of the RF front end – that’s a major milestone for the development of future antenna systems.

It’s possible that other teams will build on our foundation, which provides the essential hardware foundation for implementing the massive MIMO-based phased arrays antenna, which are required by next-generation wireless standards.

We expect our 3D stacking platform to be a transformative technology for the future landscape of global connectivity.