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IMEC Prepares The Ground For III-V Transistors On Silicon

One option for maintaining the march of Moore’s Law is to build the pairing of III-V and germanium transistors on silicon. Depositing compound semiconductors on silicon in a selective manner is tricky, but researchers at imec have shown that it is possible to do this on 200 mm on-axis wafers by forming concave trenches in the material, before filling them with a little germanium and topping them up with InP. Richard Stevenson reports.

It is getting harder and harder to squeeze more performance from silicon CMOS transistors. Back in the twentieth century improvements were possible by simply slashing the size of the silicon device and its silicon dioxide gate. But more recently gains have hinged on the introduction of exotic materials such as HfO2, which prevents an unacceptable hike in leakage currents, and the insertion of a SiGe layer to speed the passage of electrons from source to drain. Even more radical changes to the transistor architecture are on the horizon. According to the International Technology Roadmap for Semiconductors, transistor manufacture at the 11nm node, which is scheduled for 2015, will require the introduction of a new set of materials to replace silicon. III-Vs are high on the short list. If compound semiconductors are to make an impact, two tremendous obstacles must be overcome. The first is to find a pair of materials – one for the channel and another for gate – that can form a high-quality interface and prevent high leakage currents. The other challenge is to develop processes that can form III-V layers in a well-defined region on silicon substrates, so that this composite wafer could be processed in silicon foundries to yield transistors using conventional process flows and conventional toolsets. One institution that has a rich history of developing a successor to silicon CMOS and has recently been addressing both of these challenges is imec of Leuven, Belgium. Since 2007 it has been involved in ‘Dual Logic’, a project with a total budget of € 9.1 million. The primary aim of the programme is to develop transistors for logic ICs on silicon substrates that are suitable for the 22 nm node and below, and feature a germanium channel for p-type transistors and a III-V channel for n-type equivalents – both forms of device are needed to replicate silicon CMOS processors. imec has played a leading role in this project. One of its major achievements, aside from its work on germanium pMOSFETs, has been the development of processes that can form high-quality InP on selected regions of silicon substrates with the on-axis orientation used in today’s CMOS foundries. This accomplishment has required the development of techniques that form trenches with a welldefined concave base and growth processes that can fill them up with high-quality InP. The team of imec researchers began by developing InPon- silicon processes on 6° off cut, 200 mm silicon substrates in a 300 mm-compatible Crius MOCVD epireactor, built by Aixtron to be compatible with state-of-theart silicon foundry specifications (see Figure 1 for an overview of the process). Subsequently, it has transferred this technology to exactly orientated silicon (001), because it views this format as the only one acceptable to that industry. “The silicon CMOS industry is about the most conservative industry you can think of," explains Matty Caymax, head of the imec team. He points out that switching to this more common format delivered additional benefits. Growth processes on off-cut wafers led to issues of crystal quality and surface morphology that depended on trench orientation, which were avoided when using on-axis silicon. Intel continues to push the capability of silicon CMOS. It has just released second generation Intel Core i7, i5 and i3 desktop processors that are manufactured with a 32 nm process technology featuring second-generation high-k metal gate transistors. How much more can be squeezed from silicon CMOS is unclear, but Intel, like imec, is looking at III-Vs to extend the march of Moore’s Law. Credit: Intel Figure 1 (a) imec’s process flow for InP and InGaAs channel growth in silicon wafers with shallow trench isolation (b)The processes and temperatures used for InP growth Side-stepping anti-phase domains Hetero-epitaxy of III-Vs on any orientation of silicon is challenging. Accommodating lattice-mismatch between the two materials is one issue. However, this is overshadowed by problems that stem from depositing a polar material on a non-polar one. Unless the surface of silicon is carefully prepared, anti-phase domains form that plague the epitaxial layer. “The main issue with anti-phase domain boundaries is the fact that they lead to bonds like gallium-gallium and arsenic-arsenic bonds, which are rather metallic in nature" explains Caymax. “This gives you problems if you want to use these materials for electrical applications – the devices would simply short-circuit." Caymax and his co-workers initially addressed this problem by inserting a thin germanium layer in the trenches of 6° off-cut silicon. This germanium layer, which is sandwiched between silicon and InP, was treated so that all the atomic steps were two atoms high. Later, engineers replicated this landscape in the concave trenches in on axis silicon. Substantially reducing the density of anti-phase boundaries is not the only benefit of inserting a thin layer of germanium between silicon and InP. Germanium also acts a bridge between the two materials because its lattice constant is almost half way between that of silicon and InP. In addition, the germanium layer reduces the ‘thermal budget’ (the combination of high-temperatures and the length of heating time) for the pre-epi bake. A lower thermal budget is desirable, because it cuts unwanted dopant diffusion. Digging out the trenches The trenches that imec’s engineers make in the silicon substrates can have widths ranging from 20 nm to 100 μm, lengths that are an order of magnitude larger, and depths of a few hundred nanometers. They are created in wafers with the standard isolation structures known as shallow trench isolation, which are routinely used in the CMOS chip manufacturing industry. This isolation structure consists of a patterned SiO2 capping layer that can laterally isolate devices. This approach allows a straightforward and elegant integration of compound semiconductor materials in a standard manufacturing process flow as used in silicon foundries. At imec, engineers apply a standard wet clean to the wafers, dip them in hydrofluoric acid to remove native oxide and insert them into an ASM-Epsilon 2000 reactor where they are baked in hydrogen gas at 850 °C. In this chamber trenches are dug out in between the SiO2 structures by etching these silicon areas in hydrogen chloride vapour at 850°C and a pressure of 10 Torr. Before the wafers are removed, a 30-75 nm-thick layer of germanium is added at atmospheric pressure and a typical growth temperature of 450 °C. To optimise the temperature for growing the InP seed layer, imec’s engineers compared the quality of material grown at 390 °C, 420 °C and 450 °C on 6° off-cut wafers (see Figure 2). At the lowest temperature the growth proceeds by what is known as the vapour-liquidsolid regime. According to the researchers at imec, it is likely that tertiarybutylphosphine (TBP) does not decompose at 390 °C, but trimethylindium does and it forms metallic indium on the germanium surface. Catalytic decomposition of TBP then occurs on the indium droplet to create whiskers. At 450 °C, large islands form on the surface, probably resulting from an indium mobility that is too high. But at 420 °C both these issues are avoided, and it is possible to grow a relatively smooth seed layer of InP. Figure 2. There is a fairly narrow temperature window for growth of InP. (a) at 390°C it seems that only trimethylindium decomposes, forming metallic indium on the germanium surface. Catalytic decomposition of TBP then occurs on the indium droplet to create whiskers. (c) at 450°C large islands form of the surface, probably due to a high indium mobility. (b) at 420°C both these issues are avoided, and a relatively smooth seed layer of InP can be deposited Further improvements in the smoothness of this seed layer on off-cut silicon are possible by switching the gas used for the pre-epi bake from the pairing of hydrogen and TBP to hydrogen and tertiarybutylarsine (TBAs) (see Figure 3). This benefit, which has been observed before by several other groups, indicates that the quality of III-V growth is high when arsenic atoms provide a full-monolayer coverage of the germanium surface. Figure 3 Switching from tertiarybutylphosphine to tertiarybutylarsine improves the quality of the InP layer After the seed is deposited, the researchers ramp the temperature of the off-cut substrates to 610 °C over a five-minute interval that does not involve any growth of InP. This bake that takes place under a constant TBP pressure may anneal out some of the point defects and provide additional smoothening of the surface, thanks to indium migration. Engineers then deposit an InP bulk layer, using a higher growth rate than the seed. The quality of this material is improved by inserting a GaAs layer just 5 nm thick after the 420 °C bake in TBAs. The imec team have studied the quality of the InP in these trenches. In the trenches along the [110] direction it is possible to trap threading dislocations by employing an aspect ratio of more than two – if it is less than that, stacking faults and threading dislocations are seen in InP at the top of the trench. In contrast, in [110] windows in the surface, even if the aspect ratio is greater than two, stacking faults that originate at the side walls permeate through all the InP material. On the level It is possible to banish these issues related to the trench direction by turning to on-axis substrates. Modifying the trench geometry and employing similar growth processes can realise this - the only major difference to the process for the of-axis silicon is dropping the insertion of the GaAs layer. The key to success on this cut of silicon is to overetch this material during the hydrogen chloride vapour phase etch to create a concave trench. When germanium is deposited, it initially follows the underlying surface. However, when two adjacent facets interact due to the different material growth rates on different planes, the surface of the germanium film becomes smoother and its curve is not as pronounced as that at the silicon-germanium interface. imec’s engineers realize a relatively uniform step density on this germanium buffer by baking the wafer at 700 °C. At this elevated temperature the step formation energy approaches zero and the top of the germanium film becomes rounded and continuous. In addition, many single atomic steps on the curved germanium surface are converted into a smaller number of double steps. Applying this approach to the growth of InP in a 200 nm wide trench has produced encouraging results. Cross-sectional transmission electron microscopy images reveal the absence of antiphase domains in InP, which forms a flat, uniform layer along the complete length of the trench (see Figure 4). The dislocation density in the InP layer is far lower near the surface, thanks to the ‘extended defect necking effect’. Figure 4. Transmission electron microscopy images of InP grown in trenches 10 nm (a) and 200 nm (b) wide reveal how threading dislocations are confined in the bottom of the trenches Off the level When imec’s engineers set out to develop a selective area growth process for InP-on silicon, they hoped to devise a technology that could fill the trenches precisely to the top of the oxide surface. “We found that this is really challenging," admits Caymax. “We have loading effects: The growth rate and composition changes, influenced by the geometry. When you have smaller windows the growth rate goes up, when you have larger windows the growth rate goes down, and the best approach is to make sure that all the indium phosphide areas grow outside your oxide." To process such a wafer into devices, everything that sits outside the trenches must be ground away. One way to do this is chemical mechanical polishing, a technique that can ensure a smooth surface across the entire wafer. “The good thing is that chemical mechanical polishing has become an accepted step in silicon processing," says Caymax. After the CMP step, the wafers are loaded again into the MOCVD tool to top off the InP layer with the desired multiple layer stack that will form the channel of a quantum-well MOSFET. He and his team have processed some wafers with this approach, and last October they started to make their first devices. The good news is that these devices have showed transistor characteristics, but the downside is that they suffer from very high leakage currents. “We are working right now with solutions to cope with this leakage problem, one of which is the use of semi-insulating InP, which will hopefully block this leakage current," says Caymax. In terms of devices, it is clearly early days for the imec team. But the lack of transistor success to date should not overshadow the important contribution that this European institute has made to building III-V transistors on silicon: developing a novel technology to deposit high-quality InP, selectively, onto on-axis silicon wafers. © 2011 Angel Business Communications. Permission required. Further reading G. Wang et al. J. Electrochem. Soc. 157 H1023 (2010) G. Wang et al. Appl. Phys. Lett. 97 121913 (2010)

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