Reliability Physics Symposium (IRPS) Scrutinising SiC MOSFETs

Efforts by chipmakers to improve the SiC MOSFET include investigations to understand how the design of the trench influences ruggedness, the role of the substrate on device quality, opportunities for superior screening, and the origin of shifts in threshold voltage.

BY RICHARD STEVENSON, EDITOR, CS MAGAZINE

It is now 15 years since the launch of the first SiC MOSFETs by two of its pioneers, Rohm and Cree, subsequently renamed as Wolfspeed. Since then, there has been a substantial increase in the number of producers of this device, as well as an expansion in blocking voltages, improvements to performance, and a growth in sales to more than $1 billion per annum, according to many analysts.

Judged in these terms, there’s no doubt that the SiC MOSFET is already a tremendous success. But there is still more to do on many fronts. To increase the supply and trim the cost of this class of transistor, more fabs are being built, and production is switching from 150 mm to 200 mm wafers. And to improve yield, performance and robustness, many leading manufacturers of the SiC MOSFET are scrutinising its behaviour.

Figure 1. Infineon has compared the short-circuit ruggedness of MOSFETs with an asymmetric trench, a symmetric trench, and a planar trench.

At this year’s International Reliability Physics Symposium (IRPS), held in Monterey from 30 March to 3 April, researchers from a number of the leading manufacturers of SiC MOSFETs detailed insights gained from investigations into this class of transistor. Studies of short-circuit ruggedness for different channel designs were outlined by Infineon; STMicroelectronics revealed the influence of the starting material on final device characteristics; NoMIS Power presented screening methods using high gate-voltage pulses and unclamped inductive switching; and investigations into threshold voltage shift were reported by Mitsubishi Electric.

Short-circuit ruggedness
In power-conversion systems, ruggedness and reliability are critical, particularly when short-circuit events occur. Due to this, there is a need for SiC MOSFETs to be robust under repetitive fault operating conditions.

Investigating this, a team from Infineon has compared the performance of three types of SiC MOSFET produced by four different manufacturers: that with an asymmetric trench, the technology that Infineon employs; another with a symmetric trench; and two variants with planar structures with different oxide thickness (see Figure 1 for the device designs, and Table 1 for key details of the device structures).

Discussing this study at this year’s IRPS, Andrea Piccioni noted that the active areas of the MOSFETs with a trench architecture are smaller than those with a planar geometry, enabling a lower on-resistance.

Table 1. Details of the different forms of SiC MOSFET used in Infineon’s study of short-circuit ruggedness. AA is the active area, and d_GOX is the thickness of the gate oxide.

Piccioni explained that their investigation involved using normal distribution channels to purchase 15 commercial 1.2 kV devices from each of the four manufacturers. These devices, with on-resistances in the range 62 mΩ to 82 mΩ, were housed in TO247-4 pins packages, and had not been used prior to the stress test. The team decapsulated one of each of the 15 devices to analyse its characteristics in the pristine state.

The repetitive short-circuit stress test is relatively straightforward, involving the repeating of short-circuit events at a certain frequency, and ensuring that the time between each of them is long enough to avoid heating accumulation. The researchers applied 1,000 cycles at a frequency of 1 Hz, using pulses with a duration of 2 µs to provide the short-circuit. This test involved a drain-source voltage of 800 V, and values for the positive gate-source voltage varying from device to device – they ranged from 14.2 V to 15.5 V – to ensure similar values for the energy density of the four different devices.

Figure 2. The short circuit energy over 1,000 cycles reveals the superior reliability of the (a) asymmetric and (b) symmetric trench MOSFETs over their planar equivalents (c) and (d).

During testing, destructive failure can occur, due to leakage from the drain to source. In addition, there can be non-destructive failure, such as leakage from the gate to source, and variations in key characteristics, such as threshold voltage.

The team had to consider how to spot all these possible issues with one unique criterion. “We decided to use short-circuit energy variation over the short-circuit cycle,” explained Piccioni, who added that they considered a variation of more than 5 percent a failure.

Results of the stress tests show significant variation with device architecture (see Figure 2). All the MOSFETs with the asymmetric trench stay well within the ± 5 percent limit, as do those with the symmetric trench – although in that case there is a slight increase in short-circuit energy over the duration of the test, due to a negative shift in threshold voltage. In sharp contrast, the planar SiC MOSFETs performed poorly. All those with a thicker oxide failed the test, two from thermal runaway that led to destruction, and the remainder from an elevated gate-to-source leakage. The latter issue also led to the failure of ten planar devices with a thinner oxide.

Figure 3. To uncover the origin of the failure in the planar SiC MOSFETs, the team from Infineon began by removing the top-side metal and inspecting the device with a scanning electron microscope (a). Failure localisation by photo-emission microscopy followed (b) and (c), before a focused ion beam provided a cross-section (d) and its visualisation (e), exposing a short at the edge of the gate.

Piccioni also shared a Weibull plot, showing the probability of failure as a function of the number of cycles. This demonstrated that the gate oxide thickness in planar structures plays a pivotal role in robustness, within thinner oxides leading to greater reliability.

Failure analysis has been conducted by Piccioni and co-workers, initially with decapsulation and optical inspection, before removing the top side of the device and turning to scanning electron microscopy. “After that, photo-emission microscopy helped us to locate the spot where the leakage current is flowing,” remarked Piccioni, who explained that the team would then extract a cross-section, and view this using a focused ion beam. With this approach, a short is observed between the substrate and the corner of the polygate (see Figure 3).

To understand the origins of the weakness of planar devices, Piccioni and co-workers turned to Technology Computer-Aided Design (TCAD) simulations to gain an insight into the temperature profiles of different designs of MOSFET. These simulations show that compared with a trench device, that with a planar geometry has a higher temperature at the top side metallisation and at the SiC substrate. In the planar device, the hot spot occurs at 2.17 µm. Meanwhile, in the trench MOSFET, the hot spot is deeper, at 3.38 µm, reducing the stress at the gate oxide.

Figure 4. SiC substrates suffer from many types of defect.

Material considerations
A key question for the producers of any semiconductor device is this: How does the impact of the starting material influence the final device? This is far easier to answer for companies that are vertically integrated, such as STMicrolectronics, which spans powders to products.

Speaking on behalf of this European powerhouse at IRPS, Advanced Metrology Material Manager Nicolò Piluso offered some insights into this matter, by considering 650 V MOSFETs subjected to high-temperature reverse-bias tests.

SiC material is grown by physical vapour transport, with SiC powder heated at the bottom of a chamber, beneath a SiC seed crystal. The growth of SiC is imperfect, with bulk material riddled with a range of defects, including micropipes, threading screw and edge dislocations, basal plane dislocations and point defects.

Production of SiC power devices involves growth by MOCVD on substrates that are off-axis to realise the best compromise between surface kinetics and growth rate.

“The aim is to achieve a high thickness and good doping uniformity, keeping low the defectiveness,” remarked Piluso. Due to this, there’s a need for a fast epitaxial process and repeatability.

Piluso outlined how many types of defect can propagate from the substrate to the epilayer (see Figure 4). In the case of threading screw dislocations and Basal plane dislocations, growth tends to lead to a conversion into stacking faults.

Different types of defect impact the MOSFET in different ways. Micropipes, which now have a typical density below 0.1 cm^-2, are destructive, while threading screw dislocations that are accompanied by a pit, and have a similar degree of prevalence, lead to reliability issues, and can cause an increase in leakage current. MOSFETs can also suffer from a significant decline in blocking voltage, caused by in-grown stacking faults, complex stacking faults and downfalls – typical densities are 0.01 cm^-2 to 1.0 cm^-2 for the first of these, and 0.1 cm^-2 to 1.0 cm^-2 for the other two.

Figure 5. Mitsubishi Electric’s positive and negative bias temperature instability measurements were undertaken with measure-stress-measure sequences. Double sweeps of the gate voltage were performed three times to ensure a reducible readout of the threshold voltage.

Piluso explained that a number of techniques are used to follow the defectivity from the substrate to the epilayers. The most common are optical microscopy, light-scattering methodologies and photoluminescence. All three are relatively quick, have a high spatial resolution, and can uncover morphological defects, but are unable to reveal dislocations. This is possible with X-ray topography and atomic force microscopy, but both those approaches have a low throughput.

“The recent enlargement of the wafer from 150 mm to 200 mm brings several drawbacks, in terms of defects, at the beginning,” remarked Piluso. He explained that stacking faults were detected near the edge of the wafer, which is symptomatic of a physical vapour transport process issue that needs to be fixed. Another concern is scratches, due to a lack of optimisation in the chemical mechanical polishing process.

“I can say that currently, such kinds of evident defects have been almost completely removed and 200 mm high-quality silicon carbide substrates are available.”

A major weakness of today’s metrology tools is that they are unable to detect defects that lead to failure. The likes of micropipes, nanopipes and threading screw dislocations are exposed though electrical failures.

“In such cases, electrical testing is the only way to test the quality of the material,” said Piluso.

The spokesman for ST shared a map of die from a wafer, with those impacted by a defect suffering from inferior electrical characteristics, including a significant reduction in the Schottky barrier height. Raman microscopy is able to clearly identify the nature of the defect – inclusion of the 6H polytype.

Piluso also discussed electrical failure caused by a threading screw dislocation accompanied by a pit. The non-destructive optical technique emission microscopy exposed the hot spot, associated with device failure. Scanning electron microscopy then uncovered a triangular-shaped defect at this hot spot, suggesting a dislocation that originates in the substrate and propagates to the epilayer. Scrutinising this area with atomic force microscopy identified surface pitting, caused by threading screw dislocations that are clearly exposed by etching with potassium hydroxide.

The team from ST have also studied a hard failure, seen by an abrupt increase in drain leakage current after about 30 minutes. Again, emission microscopy identified the location of the device. After delayering, Piluso and co-workers applied a potassium hydroxide etch, which revealed the typical symmetry exhibited by a micropipe defect.

“It can be supposed that the defect led to a very high current density in a narrow region,” remarked Piluso, adding: “The material is brought to a high temperature, exceeding the limit imposed by conductivity, and for this reason suffered corrosion and breakage.”

Figure 6. Measurements by Mitsubishi Electric of positive-bias temperature instability reveal a shift in threshold voltage under cumulative stress that depends on the applied oxide field stress. Under high oxide stress (right), electrons injected from SiC trigger impact ionisation in the n⁺ poly-silicon, and holes that are generated are subsequently injected back into the SiO₂, where they are partially captured.

He added that scanning electron microscopy revealed a core hole in the centre of the defect at a depth of more than 30 µm, indicating that this defect starts in the bulk and goes through the entire epilayer.

When concluding his presentation, Piluso called for strong activity to improve characterisation, by enabling scanning electron microscopy, profilometery, and atomic force microscopy within standard metrology inspection at the manufacturing level.

Threshold voltage shifts
The success of the SiC MOSFET over alternatives, such as the SiC JFET and SiC BJT that got to market first, stems from providing a drop-in replacement for the silicon MOSFET. However, while both forms of MOSFET are similar, they differ in threshold voltage characteristics.

These differences in threshold voltage characteristics, seen under different temperatures and stress conditions of the oxide, are related to the SiO₂ dielectric in both types of transistor. Due to its wider bandgap, energy levels of the defects present in SiO₂ differ to those found when this oxide is paired with silicon.

Given the importance of threshold voltage – a key characteristic for any transistor – changes in the threshold voltage of SiC MOSFETs have been extensively studied. These investigations have established that the threshold voltage changes when a positive or negative electric field stress is applied to the gate oxide, as this leads to a charging of defects in the gate oxide, especially in the vicinity of the SiO₂/SiC interface.

Under a moderate electric field stress, there is a monotonic change in threshold voltage with stress time, due to the capturing of only electrons or holes, depending on the bias.

When the electric field stress is either highly positive or negative, SiC MOSFETs display a markedly different behaviour. In this case, the threshold voltage shift is initially negative, but over time it turns around and switches to positive, due to the capture of both electrons and holes in both SiO₂ and beside the SiO₂/SiC interface. Under these conditions, there’s the filling of bulk traps in SiO₂, as well as interfacial traps at or near the SiO₂/SiC interface.

According to Munetaka Noguchi and co-workers from Mitsubishi Electric, the influence of a high gate voltage on bias temperature instability of SiC MOSFETs has been well reported, accurately capturing the physical phenomena involved. “However, the impact of a high oxide electric field stress is not fully understood, and requires a systematic investigation.” So, to shed light on this issue, they have conducted a thorough study on this, reporting results for SiC MOSFETs under a range of stresses, including both high negative and positive bias, and different temperatures.

For this work, the team from Mitsubishi used vertical planar silicon-face n-MOSFETs, with the gate oxide, roughly 47 nm-thick, formed by thermal oxidation and subsequent nitridation in diluted NO. On top of the oxide is n⁺ poly-silicon.

As well as these vertical devices, Noguchi and co-workers studied lateral devices that do not have the JFET region. Investigating these lateral devices allows evaluation of the gate leakage current and the hole current flowing into the gate oxide from the channel region.

For testing both positive- and negative-bias temperature instability, for each value of threshold voltage that’s recorded, the team performed a double sweep of the gate voltage on three occasions, to ensure a reproducible readout of the threshold voltage (see Figure 5). The researchers defined the threshold voltage as the gate voltage at which the drain current reaches 1 x 10^-6 A cm^-2, and defined the change in threshold voltage as the shift in threshold voltage in the downward sweep from its initial value.

Investigations for the positive-bias temperature instability at 175 °C show that under an oxide electric field stress of 5.5 MV cm^-1, a condition referred to as ‘not so high’, there is a monotonic increase in threshold voltage with stress time, resulting from electron capture in SiO₂ (see Figure 6). But at a higher oxide electric field stress of 7 MV cm^-1, the change in threshold voltage exhibits turnaround behaviour, shifting from initially negative to positive. “This indicates that hole capture occurs initially, and after a while this process saturates, and in the following phase electron capture becomes dominant.”

The holes that are observed during this measurement possibly result from anode hole injection. This could occur under a high positive oxide electric field stress, with some electrons injected from SiC triggering impact ionisation in the n⁺ poly-silicon, and holes that are generated subsequently injected back into SiO₂, where they are partially captured.

At 175 °C, under an oxide electric field stress of 7.4 MV cm^-1, the negative change in threshold voltage is larger than it is at 25 °C, suggesting that at a lower temperature more holes are captured by SiO₂.

To delve deep into electron capture, Noguchi and co-workers have studied the change in threshold voltage after turnaround, which is considered at the starting point for these measurements. Plots (see Figure 7) show that in the region where the shift in threshold voltage is less than 0.2 V, the curves for different oxide electric field stresses have an almost parallel shift, with the slope becoming more gradual as time increases.

Figure 7. Measurements of the shift in threshold voltage after turnaround can be categorised into: curves with an almost parallel shift, with the slope becoming more gradual as time increases, suggesting the presence of as-grown electron traps in SiO₂; and curves that get steeper with time, suggesting the generation of as-grown electron traps in SiO₂ and/or the interfacial region.

According to the team, this gradual saturation suggests the presence of as-grown electron traps in SiO₂. Meanwhile, where the shift in threshold voltage is more than 0.4 V, the slope becomes steeper with time, suggesting the generation of as-grown electron traps in SiO₂ and/or the interfacial region.

The team have also investigated the impact of the starting gate voltage on the change in threshold voltage after turnaround, comparing plots for 0 V and -7 V. Under the same oxide electric field stress, the change in threshold voltage is larger for 0 V, implying greater capture of electrons in SiO₂. This may occur because the surface potential at SiO₂/SiC is more bent at -7 V, leading to efficient emission of captured electrons.

Noguchi and colleagues have also carried out a thorough study of the shift in threshold voltage under stress under a negative bias. Similar to under positive bias, the plots at 175 °C vary with the oxide electric field stress: there’s a monotonic decrease observed at -5.8 MV cm^-1, due to hole capture in SiO₂; and, under -7.5 MV cm^-1, a turnaround from a decrease to an increase, attributed to electron capture in SiO₂ and/or near the interface between SiO₂ and SiC (see Figure 8).

Figure 8. Negative bias temperature instability measurements by Mitsubishi Electric reveal a shift in threshold voltage under cumulative stress that depends on the applied oxide field stress. The turnaround from a decrease to an increase in threshold voltage under -7.5 MV cm^-1 is attributed to electron capture in SiO₂ and/or near the interface between SiO₂ and SiC.

Previous studies on hole injection into SiO₂ on silicon have shown that the build-up of negative charges can be attributed to the generation of electron traps in SiO₂ and/or interfacial traps at the interface between SiO₂ and SiC.

Under a negative oxide-electric-field stress, holes injected from SiC are captured by SiO₂. It’s possible that these injected holes could generate electron traps in SiO₂ and at the interface.

“To understand the phenomena, it’s helpful to start the discussion with a threshold voltage shift at lower temperatures, such as 25 degrees C,” remarked Noguchi.

Plots of this behaviour show a saturation in threshold voltage shift for all the applied oxide electric field stresses, which range from -5.8 MV cm^-1 to -7.9 MV cm^-1 (see Figure 9). At a higher oxide electric field stress, the change in threshold voltage is accelerated, attributed to faster hole capture.

Investigating the change in threshold voltage at -7.5 MV cm^-1 for a range of temperatures shows that the minimum value does not change, and it is reached more quickly at higher temperatures, due to as-grown hole traps being filled more quickly, without additional generation of hole traps. Turnaround from a negative to a positive change in threshold voltage does not occur at 25 °C, but does at 125 °C and 175 °C.

Noguchi and co-workers have investigated the change in threshold voltage after turnaround at 25 °C and 175 °C. “At both temperatures, the threshold voltage shift after turnaround can be universally described by the gate-injected charges after the turnaround,” remarked Noguchi, who pointed out that the shift is smaller at the lower temperature, and that the electron capture component of the threshold voltage shift can be attributed to the electron traps in silicon dioxide and at the interface.

To investigate these interfacial electron traps, the team studied the sub-threshold swing as a function of gate-injected charges. They found two phases in the generation of interfacial electron traps. “This indicates that the generation of interfacial electron traps on the negative oxide electric field stress partially contributes to the threshold voltage shift after turnaround.”

Figure 9. Saturation of the threshold voltage shift, attributed to hole capture, is faster under a higher oxide electric field stress.

Screening SiC MOSFETs
Over the last decade, advances in SiC substrates, epitaxial growth and the gate oxidation process have improved gate oxide reliability, but the risk of extrinsic failure in SiC devices still persists. This is an issue for the adoption of SiC MOSFETs in the electric vehicle market.

To address this concern, manufacturers of SiC power devices employ burn-in, at the package or wafer level, to provide a reasonable reduction in the ‘failure-in-time’ (FIT) rate – it’s the number of failures per billion hours. For this task, harsher burn-in conditions enhance screening efficiency and further reduce the FIT rate, but may induce parametric shifts in the devices. What’s more, the use of high-temperatures and extended testing during burn-in leads to a hike in overall production costs.

Due to these concerns, there is much interest in approaches that can cut the cost and time required to screen SiC MOSFETs.

One company developing a solution to this that’s based on high gate-voltage pulses and unclamped inductive switching is NoMIS, a spin-off of the University at Albany, New York, that manufactures 1.2 kV, 1.7 kV and 3.3 kV SiC MOSFETs with worldwide foundry partners. Speaking on its behalf at this year’s IRPS, Head of SiC Device Development at NoMIS Power, Seung Yup Jang, described this effort, which also involves contributions from the University at Albany and The Ohio State University.

Jang explained that unclamped inductive switching is an effective method for identifying early failures under off-state high drain bias. While originally designed to evaluate edge termination robustness, uniform avalanche current distribution in active cells, and suppression of the parasitic bipolar junction, it has broader utility. During avalanche breakdown the maximum electric field in the gate oxide will typically exceed 3 MV cm^-1, and may be as high as 4 MV cm^-1. If a negative bias is applied during unclamped inductive switching, the oxide electric field can be even higher, causing the temperature in the active region to rise, often exceeding 500 °C. “These extreme conditions impose considerable stress on the gate oxide, making unclamped inductive switching a rigorous and informative screening method.”

The team has developed an approach that aims to screen out all early failures using regular, automatic testing tools, as this is a cost-effective and efficient approach. The combination of high gate-voltage pulse screening and unclamped inductive load screening has been evaluated twice – after wafer fabrication and after packaging.

For this study, Jang and co-workers have investigated 1.2 kV, 35 mΩ and 80 mΩ planar SiC MOSFETs produced in a commercial foundry using 150 mm wafers. Gate oxides were thermally grown on 4H SiC substrates, with interface quality improved with post-oxidation annealing in nitric oxide.

To evaluate the gate oxide lifetime distribution of devices without any screening process, the team conducted constant-voltage time-dependent dielectric breakdown (TDDB) tests on 80 devices from each group.

Some devices in the 35 mΩ group failed instantly during TDDB testing, as the voltage ramped up, indicating infant failure, despite having passed prior DC testing under positive 5 MV cm^-1 and negative 2 MV cm^-1 pulsed gate-bias conditions.

Table 2. NoMIS has screened SiC MOSFETs using high-voltage pulsed (HVP) and unclamped inductive switching (UIS) tests.

To develop an effective screening method that minimises stress and duration conditions while addressing infant gate oxide failures, Jang and co-workers applied various screening conditions to their 35 mΩ devices (see Table 2 for details). The high-voltage pulse test conditions were devised to avoid severe degradation to the threshold voltage while providing sufficient stress, and unclamped inductive switching conditions delivered a fraction of the maximum single-event avalanche energy.

The team’s testing sequence began with an initial DC test, and then more than 100 functional 35 mW devices were subjected to the various screening tests. 80 devices passed a second DC test, and were then subjected to TDDB tests using 9 MV cm^-1 at 150 °C.

Results of the tests (see Figure 10) show that high-voltage pulse tests produce a shift in threshold voltage of up to 5 percent, attributed to impact ionisation in the oxide and trapping of holes in the SiO₂ and at the SiO₂/SiC interface. “This is an undesirable effect, as it may lead to the generation of new defects, and the negative threshold voltage shift is relatively permanent,” remarked Jang. In comparison, the unclamped inductive switching test had a smaller impact on threshold voltage.

The changes in on-resistance mirror those in the shift in threshold voltage, but are less than 1 percent; and the avalanche breakdown voltage (BV_DSS) and drain-to-source leakage (I_DSS) do not show consistent trends.

“Overall, with the exception of the threshold voltage shift, the major parameter changes appear to be negligible,” said Jang.

According to hysteresis measurements, there is no noticeable degradation of the SiO₂/SiC interface associated with the screening tests.

Figure 10. NoMIS has undertaken a range of screening tests: (a) threshold-voltage shift; (b) on-resistance shift; (c) avalanche breakdown voltage; and (d) drain-to-source leakage.


Jang and co-workers have undertaken constant-voltage TDDB tests of devices that have undergone screening, to see if this impacts infant failure, extrinsic failure, and intrinsic lifetime of the gate oxide. These investigations found that: screening did not degrade the intrinsic lifetime of the gate oxide; that after unclamped inductive switching, one infant failure in 80 devices occurred; and that no infant failures occurred after high-voltage pulse tests.

“It should be acknowledged that a sample size of 80 devices is insufficient to make definitive conclusions regarding statistical distributions, [but] the combined results from both the unclamped-inductive-switching-tested and the high-voltage-pulse-tested groups allow for a qualitative interpretation,” argued Jang. “Specifically, unclamped inductive switching alone cannot screen out infant failures,” added Jang, who pointed out that direct gate stressing under high-voltage pulse conditions proved to be more effective.

When it comes to extrinsic failures, the screening tests are not that effective, warned Jang, who added that only the HVP3 condition has a positive influence – that involves applying a field of 8.6 MV cm^-1 for 1 s.

To avoid excessive negative shifts in threshold voltage and minimise excessive stress associated with unclamped inductive switching, Jang and co-workers adopted the ‘combo’ condition (defined in Table 2) for baseline screening. They used this to test a larger sample size, consisting of 1,607 MOSFETs with an on-resistance of 30 mΩ, and 2,798 with an 80 mΩ on-resistance.

Results (see Figure 11) show that the I_DSS criteria effects the screening rate. Many failures of high I_DSS devices during HVP1 and unclamped inductive switching indicate that leaky devices are vulnerable not only to unclamped inductive switching, but also gate oxide reliability.

Figure 11. A comparison of the screening rate with tight and relaxed I_DSS unclamped inductive switching criteria.

Jang and colleagues have speculated that it is local defects, which contribute to a high I_DSS leakage, that are responsible for failures during both the high-voltage pulsed and unclamped inductive switching tests, as these defects may lead to non-uniform gate oxide formation and a non-uniform avalanche current distribution. The team plans to investigate this matter.

The use of a tighter condition for screening (see Figure 11) produced a yield drop of around 1 percent compared with the more relaxed variant. According to the team, this is a small trade-off against the benefit of screening-out potential risk factors.

These insights into screening, along with the greater knowledge of the impact of oxide electric field stress, substrate material and gate oxide architecture, will help to refine the production of SiC MOSFETs. As well as the increase in availability over the coming years, customers are destined to get their hands on better products.