Tower and Cadence Announce Flow for 5G and Automotive chips
Flow showcases advantages of a unified design environment for chip and package co-design and simulation
Cadence Design Systems and Tower Semiconductor have announced the release of a silicon-validated SP4T RF SOI switch reference design flow using the Cadence® Virtuoso Design Platform and RF Solution. The reference design flow provides a faster path to design closure for advanced 5G wireless, wireline infrastructure, and automotive IC product development.
This new RF reference design flow leverages a comprehensive set of mixed-signal and RF design, simulation, system analysis and signoff tools that are tuned for Tower’s CMOS, BiCMOS, SOI and SiGe process technologies. Using the new offering, joint customers can accelerate RF, mmWave and high-performance analog designs and increase signoff confidence.
“This unique RF and mmWave full-flow solution has been jointly validated on Tower’s CS18 RF SOI foundry process,” said KT Moore, vice president, product management in the Custom IC & PCB Group at Cadence. “Our ongoing partnership with Tower has generated yet another highly beneficial solution, enabling advanced IC design, which meets the requirements of today’s most complex systems. Cadence and Tower customers benefit from an integrated workflow using an all-Cadence toolset and a Tower reference design to rapidly develop compelling products.”
Tower’s RF and high-performance analogue design enablement solutions, PDKs and reference flows complement its best-in-class foundry wireless and wireline process technologies, including the CS18 and TPS65RS for RF-SOI and SBC18 for SiGe BiCMOS. RF and mmWave IC and package co-design has been a critical issue for Tower’s customers, and they are now armed with silicon-validated tools and flows. Joint customers can design differentiated ICs optimised for cost and performance.
“We are excited to announce the expansion of our design enablement capabilities, providing our customers with new competitive advantages,” said Mr. Ori Galzur, Tower Semiconductor VP of VLSI Design Center and Design Enablement. “Through our long-term collaboration with Cadence, a world-leading provider of highly advanced design tools, we are able to continuously deliver new and advanced design tools with unique features that best suit IC design requirements in leading markets, providing our customers with fast and accurate design cycle time.”
As frequencies move higher, the need for accurately incorporating multiphysics effects grows. As such, the RF and mmWave PDKs available from Tower now incorporate the Cadence Celsius Thermal Solver, EMX Planar 3D Solver and Clarity 3D Solver technologies to seamlessly account for electromagnetic (EM) and thermal integrity of the design.
The multiphysics analysis products complement the existing Cadence toolset in use at Tower, including the Virtuoso environment, Spectre® Simulation Platform, Quantus Extraction Solution, integrated Litho Physical Analyzer, and Innovus Implementation System.
