IEDM: Turbo-charging the transistor

At a session at the International Electron Devices Meeting devoted to 6G and terahertz applications, engineers unveiled new strategies for increasing the operating frequency of the transistor.

BY RICHARD STEVENSON, EDITOR, COMPOUND SEMICONDUCTOR

As the roll-out of 5G gathers pace, engineers in academia and industry are considering what might follow. Towards the end of this decade and beyond, wireless communications is tipped to move to higher frequencies – almost certainly beyond 100 GHz, and possibly encroaching the terahertz domain.

While the next step on the wireless roadmap, 6G, is yet to be defined, it is expected that initial research into this communication standard will focus on the D-band, which spans 110 GHz to 175 GHz. However, when 6G is actually deployed, it is likely to operate within the 300 GHz to 450 GHz frequency range. Circuits operating at such high speeds will need to combine high frequencies with a high power efficiency and multi-functionality, a set of conditions that is hard to satisfy with silicon CMOS. Offering more promise are heterogeneous technologies that marry the merits of silicon, such as maturity and high-volume manufacture, with the superior speeds of the III-Vs.

Efforts in this direction were discussed in session at the 2021 International Electron Devices Meeting (IEDM) entitled Microwave, Millimetre Wave and Analog – III-V technologies and their application to terahertz/6G. In that session, taking place in San Francisco in early December, Intel championed its record-breaking enhancement-mode GaN transistors produced on 300 mm silicon, and a team led by KAIST claimed to break new ground with InGaAs HEMTs on silicon. Other teams reported their successes with III-V transistors on native substrates, potentially providing a stepping-stone to triumphs on a silicon foundation. A partnership between engineers in South Korea and NTT detailed InGaAs-on-InP HEMTs with record-breaking frequencies, while researchers at ETH Zurich unveiled terahertz transistors based on GaAsSb and InP that are fabricated with a new process that provides optimisation of the base-emitter access distance.

Figure 1. (a) Intel’s E-mode GaN transistor has an f_T of 300 GHz and an f_MAX of 400 GHz. (b) A transmission electron microscopy image shows the gate length is just 29 nm.

Intel integration
At IEDM Intel made many record-breaking claims for its GaN-on-silicon transistors, including new benchmarks for the cut-frequency (fT) and maximum oscillation frequency (f_MAX), two key figures-of-merits. Further firsts included: the highest transconductance, attributed to device scaling and the incorporation of a material with a high dielectric constant; a record-breaking drain-source voltage for this class of transistor; and the fabrication of the first truly E-mode GaN transistor that delivers a full on-current, realised with a record low-gate drive of just 1.8 V (typically, E-mode GaN HEMTs need a gate drive of at least 6 V). In addition, Intel’s GaN-on-silicon transistors were said to provide an outstanding RF performance.

According to Han Wui Then, spokesman for the Intel team from Hillsboro, Oregon, their successes have come from insights provided by Moore’s law and Dennard MOSFET scaling. To draw on this, they developed a process for producing E-mode transistors with gate lengths down to 30 nm. Their fabrication involves the use of a high-k dielectric technology, an atomic layer etch, and GaN buffer technology.

Intel’s spokesman is in no doubt that the best material system for such efforts is GaN, describing this as “the technology of choice for ultra-fast switching and for producing compact integrated power electronics and RF millimetre-wave”.

The team’s GaN transistors, formed on silicon (111) substrates, feature a recessed gate and low-resistance re-grown source and drain contacts (see Figure 1 for a device diagram). Circuits that incorporate these devices are formed with a four-level copper backend interconnect process that can produce thin-film resistors and metal-insulator-metal capacitors (see Figure 2).

Figure 2. (a) Intel’s high-speed ICs are formed using a four-layer copper back-end stack that includes metal-insulator-metal capacitors and thin-film resistors. (b) A scanning electron microscopy image, showing the fabricated copper backend interconnect over E-mode high- dielectric GaN transistors fabricated on 300 mm silicon.

“Our 300 millimetre process is highly uniform,” argued Then, who pointed out that the one-sigma variation in threshold voltage is just 38 mV. He added: “This enabled us to fabricate and integrate a large number of gates”. He gave an example of a power GaN die with a total width of 880 mm and an area of just 4 mm². This chip is capable of a power density of 9 A mm-^2.

Attributes of Intel’s GaN transistors include a very low leakage current, a high drive current, a low on-resistance, and a capability to withstand a drain-source voltage up to 65 V. A common figure-of-merit for power electronics – the product of on-resistance and the gate charge – suggests that Intel’s GaN transistors are 14 times better than discrete GaN and silicon LDMOS devices (see Figure 3). “This gain truly shows the power of scaling when applied to high-k gate dielectric gallium nitride transistors,” claimed Then. Intel’s GaN transistors combine an impressive performance with a high level of reliability. Operating at 90 °C with a drain-to-source voltage of 10.5 V, time to failure – defined as a degradation in the drain current by 10 percent – is 10 years.

Figure 3. Channel length scaling improves the power delivery switch, according to a figure-of-merit that is defined as the product of on-resistance and the gate charge. One of the benefits of scaling is that it allows the construction of faster, more compact power electronics.

Studies by Then and colleagues have shown that shrinking device dimensions leads to a hike in transconductance. Decreasing the gate length from just over 2 µm to 30 nm led to a rise in transconductance from just over 1200 µS/µm to 2100 µS /µm.

Transistors with a 30 nm gate length and a gate-to-drain distance of 160 nm have an fT of 300 GHz and an f_MAX of 400 GHz. For this device, the RF switch figure of merit – the product of the on-resistance and off-capacitance – is 70 fs. This as an “excellent number,” said Then.

He and his co-workers have also carried out load-pull measurements, considering a range of frequencies and various gate lengths. Results included a device with a 90 nm gate length producing an output power of 23.4 dB at 28 GHz, alongside a power density of 2.7 W/mm and a power-added efficiency of 50 percent. Increasing the frequency led to a reduction in output power and efficiency, with a saturated output power falling to 0.4 W/mm at 90 GHz, and power-added efficiency down to 10.5 percent.

The team from Intel are expecting GaN finFET architectures and 3D layer transfer technologies to play a significant role in the scaling of GaN transistors and the integration of more functionalities. According to Then, this could include a marriage of GaN and CMOS, to enhance the capabilities and reach of GaN technology.

He and his co-workers have already started to explore this possibility, using 3D layer transfer technology to unite silicon PMOS and GaN NMOS devices (see Figure 4). The latter, having finFET widths of just 35 nm, are claimed to feature the narrowest GaN fins ever produced. Device fabrication involved the bonding, cleaving and transfer of a thin layer of single-crystalline silicon onto a GaN transistor wafer, prior to completing the fabrication steps required to form the top silicon devices over the bottom GaN transistors.

Figure 4. (a) Using wafer bonding, a team from Intel produced a 3D-stacked GaN-silicon CMOS inverter. Transmission electron microscopy images show: (b) the stacked inverter, comprising a bottom GaN E-mode high-k NMOS finFET and a top silicon PMOS finFET; (c) a 35 nm-wide silicon fin, which forms the top PMOS channel; and (d), a 25 nm-wide GaN fin for the bottom NMOS channel.

According to Then, initial results are promising, with the hybrid structure producing low leakage currents, a pre-requisite for logic applications. Another attribute is a well-matched threshold voltage between the finFETs of silicon PMOS and GaN NMOS.

InGaAs attributes
Heterogenous 3D integration also featured in a presentation from Jaeyong Jeong from KAIST, who argued that there is still work to do before this technology can target 6G applications. When discussing the improvements that are needed, he honed in on the need to increase f_T and f_MAX and to minimise self-heating. “We need new monolithic 3D structures for relaxing self-heating of top devices.”

To address these issues, the team from KAIST improved the f_MAX of their transistor by gate scaling and process optimisation, and introduced a novel monolithic 3D structure with a back metal that quashes self-heating. Success came from using indium-rich InGaAs HEMTs – they offered the best balance of f_T and f_MAX to date, as well as the lowest noise figures.

The team’s latest triumphs have built on previous work, reported in 2021, that resulted in an f_T of around 450 GHz. However, the accompanying f_MAX of 210 GHz, attributed to a lack of optimisation, needed to increase. The team also identified a need to address the impact of heat dissipation by an inter-layer dielectric. This could degrade performance and reliability.

Jeong and co-workers tackled all these concerns by fabricating a monolithic 3D structure that did not suffer from a substantial degradation in RF performance when inserting a metal backside on top of the RF devices (see Figure 5) .

Figure 5. Engineers at KAIST are pioneering a heterogeneous, monolithic 3D analogue/RF-digital mixed-signal platform. (top) A back metal is included to reduce self-heating. (bottom) Cross-sectional transmission electron microscopy images show the global back metal, the III-V HEMT, and the SiO₂ interlayer dielectric.

To form this superior structure, the team loaded InP substrates into an MBE reactor and grew an inverted HEMT heterostructure featuring a channel comprising a 3 nm-thick layer of InAs, sandwiched between a pair of 3 nm-thick In_0.53Ga_0.47As layers. The next steps involved depositing a 40 nm-thick layer of SiO₂ on the silicon wafer, adding a patterned 40 nm-thick back metal, and covering this in a 600 nm-thick interlayer dielectric. Subsequent chemical mechanical polishing eliminated the step height and ensured the desired thickness for this dielectric layer.

A wafer-bonding process followed, involving the addition of 20 nm-thick layers of Al₂O₃ to both silicon and InP wafers. Once they were brought together, highly selective wet etching removed the InP substrate and the etch-stop layer, before molybdenum-based source and drain contacts were added and double-exposure e-beam lithography formed a 95 nm gate foot opening and a wide head. The final steps involved the use of citric acid to etch the n+ In_0.53Ga_0.47As layer, forming a T-gate by a deposition and lift-off process, and annealing the structure at 300 °C for 5 minutes.

Measurements on a device with a gate length of 95 nm and a gate width of 2 x 20 µm revealed an f_T of 301 GHz and an f_MAX of 716 GHz – the latter is claimed to be a record for monolithic 3D transistors. The researchers found that increasing back gate bias led to a slightly higher f_MAX, thereby providing enhanced flexibility to circuit design.

Thermal analysis revealed that self-heating is asymmetric, with more heat generated by the drain side (see Figure 6). According to high-resolution thermoreflectance microscopy, despite the poor thermal conductivity of the InGaAs channel compared with that made from silicon, the former has a 1.8 times smaller thermal resistance, thanks to the Al₂O₃ layer.

By comparing different device designs, Jeong and co-workers discovered that the addition of a local back metal decreased the thermal resistance by 19 percent compared with a device without a back metal. Turning to a global back metal provided a 31 percent improvement.

Although the insertion of a back metal introduced additional parasitic capacitance, this did not have a significant impact on f_T and f_MAX. As the reduction in these values is less than 7 percent, the slight reduction in RF performance can be compensated by adjusting the back gate bias.

Efforts to improve InGaAs quantum well HEMT technology have also been undertaken by a collaboration between engineers at NTT, Japan, and three institutions in South Koera – Kyungpook National University, the University of Ulsan and Quantum Semiconductor Incorporation (QSI). This partnership has combined the fabrication of record-breaking HEMT designs with the development of accurate mathematical models, which have been lacking. The team’s new physics-based models can predict f_T and f_MAX using just the physical and geometrical parameters of apparent mobility, saturation velocity and aspect ratio.

Figure 6. (a) Engineers at KAIST produced a variety of monolithic 3D RF transistors with different back metal structures. (b) Cross-sectional scanning transmission electron microscopy images and (c) CCD images of these back metal structures. (d) Thermal images of these different structures reveal that the architecture has an significant impact on self-heating.

The portfolio of devices for this work included those with a cap recess etched, to accommodate transfer-length-method measurements; and those with gate lengths from 10 µm to below 30 nm, a range spanning the mobility relevant regime to the ballistic regime. An i-line stepper defined longer gates, while shorter variants were formed with electron-beam lithography. Most epilayer designs were produced on InP. They included devices with a 15 nm-thick In_0.53Ga_0.47As quantum well, a 10 nm-thick In_0.7Ga_0.3As quantum well, a 7 nm-thick In_0.8Ga_0.2As quantum well, and an In_0.53Ga_0.47As/In_0.8Ga_0.2As/In_0.53Ga_0.47As quantum well with a thickness of 8 nm. In addition, the team used a GaAs substrate to produce a HEMT with a 10 nm-thick In_0.7Ga_0.3As quantum well (Figure 7 details all the epistructures).

Figure 7. A collaboration between researchers in Korea and Japan has produced a portfolio of devices with different hetero-structures and gate lengths.

Speaking on behalf of the team at IEDM, Hyeon-Bhin Jo from Kyungpook National University detailed the record-breaking results, as well as providing an overview of progress in the performance of f_T and f_MAX. He pointed out that up until the early 1990s, increases in the f_T and f_MAX of III-V HEMTs were driven by scaling the gate length to below 100 nm, while from the mid 1990s to 2010, further increases in f_T came from enhanced transport, using indium-rich quantum-well channels.

“From 2010 to now, reductions in parasitics, such as series resistance and parasitic capacitance, have increased f_T, whereas there has been no further improvement in f_MAX – it has actually degraded.”

Addressing this weakness, HEMTs produced by the team combine a high f_T with a high f_MAX, with both values benefitting from gate scaling. Plots presented by Jo show that the composite HEMT produced the best results, thanks to a superior average velocity in the In_0.53Ga_0.47As/In_0.8Ga_0.2As/In_0.53Ga_0.47As channel. For that design, a device with a 30 nm gate length combined an f_T of 706 GHz with an f_MAX of 962 GHz. “f_T continues to increase with gate length decrease,” added Jo. “Contrarily, f_MAX shows its peak at a gate length of 30 nanometres, and decreases.” According to him, the reason for this is the intrinsic output transconductance, which plays a more critical role for gate lengths less than 100 nm.

Jo and co-workers have benchmarked their results, considering f_T, f_MAX, and the average of these two figures of merit (see Figure 8). “The result for the composite channel HEMT shows the best balance and the highest average frequency for any transistor technology for all gate lengths.”

Figure 8. The collaboration between researchers in Korea and Japan has produced InGaAs quantum-well HEMTs with impressive values for the average of f_T and f_MAX (a) and for f_MAX (b).

Type-II triumphs
An attractive alternative to transistors made from GaN and from GaInAs is the combination of InP and GaAsSb. This pairing can unite to form a type-II double HBT that is free from electron blocking and provides a conduction band offset of around 150 meV between the GaAsSb-base and the InP collector.

Driving recent improvements to this particular device is a team at ETH-Zurich headed by Colombo Bolognesi. At IEDM, Akshay Mahadev Arabhavi spoke on behalf of this group, outlining a new fabrication technique that has led to record-breaking performances, including an f_MAX of 1.2 THz and a very high figure for the open base common-emitter breakdown voltage.

The latest work builds on previous results, which included an f_T of more than 450 GHz, an f_MAX in excess of 800 GHz, and a breakdown greater than 4.5 V. “In addition, and more importantly, these devices [from before] have a very good power performance,” remarked Arabhavi, giving the example of an output power of more than 1 mW/mm at 94 GHz, alongside 12 dB of linear power gain and a maximum power-added efficiency of 30 percent.

The team’s latest devices employ a new architecture that features a fin emitter and ensures a reduction in extrinsic base-collector parasitics. This comes from a reduction in the emitter-base access gap, realised without having to reduce the base metal thickness. “In fact, we have an even thicker base metal contact than before,” argued Arabhavi, who added that the new design also offers control over the base metal contact width. This allows a reduction in the area of the junction and ultimately the extrinsic capacitance.

The team from ETH used MOCVD to grow the heterostructure for the HBT. Compared witth the previous design, the thickness of the InGaAs emitter contact has been reduced from 35 nm to 10 nm and the heavily doped InP emitter thinned from 130 nm to 20 nm. Due to these changes, the total emitter thickness has been slashed from 185 nm to 50 nm. Note that the base and collector dimensions have not been changed.

Figure 9. The team at EPFL forms it record-breaking double HBTs with a process that allows an optimal choice of base-emitter access distance down to 10 nm, the use of thick base contact metals, and minimization of parasitic capacitances and resistances via precise lateral wet etching of the base-collector mesa. The steps used are the formation of: (a) the emitter metal; (b) the emitter fins, using a trilayer photoresist; (c) the emitter mesa; (d) the self-aligned base contacts, and AlO_x passivation; and (e), the narrow base-collector mesa.

Fabrication of the emitter-fin double HBT involved e-beam lithography and deposition to form an emitter metal structure, followed by argon sputtering, which simultaneously etched the GaInAs contact layer and smoothed the emitter metal edge roughness. A trilayer photo resist process followed, to form fins and set the base access distance, thanks to self-alignment (see Figure 9 for details). The final steps involved: the addition of a passivation layer; wet etching, to create a base-collector mesa; and a low-temperature etch-back planarization process, to support the electron-beam evaporated probe pads.
Arabhavi and co-workers made DC measurements on devices with a 35 nm base access distance and an emitter area of 0.25 µm by 4.4 µm. For collector currents of 1 kA cm-² and 10 kA cm^-2 – two common values for benchmarking – the common-emitter breakdown voltages were 5.4 V and more than 6.5 V.

For RF measurements on double HBTs, the team found that a variation in collector current produced changes to values for f_T and f_MAX. Using a collector-emitter voltage of 1 V, both frequencies peaked at a collector current density of around 9.2 mA mm^-2, with f_MAX hitting 1.2 THz and f_T climbing to 475 GHz.

The team also studied the values of f_T and f_MAX for a range of collector currents and emitter sizes (see Figure 10). Even devices with a 9.4 µm-long emitter had an f_MAX of more than 1 THz.

Figure 10. Engineers at EPFL have shown that even for an emitter mesa length as long as 9.4µm, f_MAX can exceed 1 THz. This result is claimed to emphasize a breakthrough in scalability.

“This is a significant breakthrough in HBT scalability,” argued Arabhavi, who believes these high values for f_T and f_MAX, along with the high breakdown voltage, make the ETH devices very promising (see Figure 11).

Figure 11. Benchmarking double HBTs, with colour-coded breakdown voltages. The team from EPFL is claiming a new milestone for a f_MAX x VCEO of 6.48 THz V.

Thanks to this breakthrough, and those unveiled by other teams developing ultrafast transistors and ICs, foundations are being laid for communication at 6G and beyond. While it may be difficult to know quite what will follow with such fast data communication rates, we can be sure to expect that life in the virtual world has an exciting future ahead – and one that we will hopefully benefit from.