Gearing up for electric vehicles with Soitec’s SmartSiC substrates

Offering a ten-fold reuse of single-crystal SiC and a ten times better conductivity than its conventional counterpart, SmartSiC is poised to revolutionise the production of power electronics for electric vehicles and industrial applications.

BY OLIVIER BONNIN, ERIC GUIOT, WALTER SCHWARZENBACH, NOÉMIE BALLOT AND CÉLINE TRANQUILLIN FROM SOITEC

If humankind has one task of utter urgency it is the reduction of carbon dioxide emissions. Following decades of spiralling emissions, we are now living in an age of catastrophic environmental and demographic damage, and without drastic action this situation is only going to get worse.

A significant share of today’s greenhouse gas emissions come from transportation, traditionally a significant polluter. But this sector is embarking on a once-in-a-century transformation, driven by researchers, industries, institutions and customers – all stakeholders in the transportation ecosystem – coming together to shape a greener future. Sitting at the very heart of this industrial revolution are electric vehicles, the key driver to slashing carbon dioxide emissions associated with mobility.

Fuelling the uptake of the EV are falling prices, longer driving ranges and rapid charging times. Crucial to further advances in performance, which will spur sales to reach new heights, is the optimisation of the powertrain. It’s a task attracting intense, cutting-edge R&D. In every EV the direct current from the battery is transformed into an AC form that drives the traction motors. The efficiency of the inverter that performs this function governs the efficiency of the drivetrain – increasing this is essential for improving EV performance..

Tesla, the world-famous pioneer of the EV, started introducing SiC devices into its vehicles in 2018. Since then, devices made from this wide bandgap semiconductor have been the undisputed and optimal choice for managing power conversion in drivetrains and on-board chargers. Note that the compelling case for SiC is only going to strengthen when the EV industry shifts from 400 V to 800 V systems for fast chargers. Due to this, penetration of SiC-based devices in EVs is to climb over the next decade from 30 percent to 70 percent, against a backdrop of an ever-increasing number of vehicles sold per year (see Figure 1).

Figure 1. Global EV’s market trend and SiC penetration.

With penetration of SiC-based devices and technologies climbing fast and EV sales skyrocketing in all major geographies, streamlined SiC supply chains are essential. Many power device manufacturers are fully aware of this need, and are responding with strategic moves, either investing in high-volume wafer manufacturing capabilities, or building vertical integration models and making strategic acquisitions to solidify supply chains.

While a shift to SiC may seem radical to some, the technology has in fact had an intensive maturation period with experts anticipating its arrival to the mass market for years. It’s been just over 20 years since it emerged as a disruptive alternative to silicon in the power electronics industry. While chipmaking is more expensive and requires a more complex manufacturing process, this must be weighed against the increase in energy conversion efficiency. Over the last two decades, the cost of making SiC devices has fallen, partly through a migration from 25 mm wafers to ever larger diameters, with 200 mm now at the leading edge. Such gains have propelled the benefits-to-cost ratio for SiC to a level where there is no longer any discussion of whether this material is suitable for EVs. The breakthroughs have ensured that the SiC industry is an incredibly dynamic market, in terms of growth and design opportunities.

Yet despite all this promise and initial success, SiC has remained, until recently, a material that just serves in the high-end industrial sector, as well as other power-conversion applications. Expansion of the market has been hampered by a relatively narrow product offering from device manufacturers. There are only a few devices that have been specifically designed for EV applications, and their manufacturing yield has been compromised by the defectivity levels found in standard SiC wafers.

A physical barrier to realising a higher manufacturing yield is the range of intrinsic defects that arise during the manufacture of SiC boules using the incumbent process, physical vapour transport (PVT). These imperfections in the material prevent device manufacturers from hitting the required yield, causing chip production to be economically unviable. Yields are hampered by the large size of the chips. SiC MOSFETs with a unitary surface of at least 40mm² are required to ensure the handling of currents of 200 A, which are needed for the power levels of the EV traction inverter.

SmartSiC: the cutting-edge solution
Addressing this challenge is SmartSiC, the game-changing technology from Soitec. This is the latest expansion of our Smart Cut portfolio. Within this family, we ship more than 2 million wafers per year to a variety of product lines, including those for making devices for smartphones. It’s a success story that has led us to be the largest pure-play supplier of engineered substrates for radio-frequency and mobile phone markets. Over the last few years we have laid the foundations to repeat that success in automotive and industrial markets with SmartSiC.

Drawing on 30 years of expertise with our Smart Cut process, through our SmartSiC wafers we offer a new and disruptive engineered substrate. This building block for making SiC devices introduces a new paradigm for the electrical performance of the wafer, the productivity of the supply chain, and the device power density. Merits of this engineered wafer, which creates significant value at both the device and the system level, include easing the adoption of eMobility and enabling enhancement of charging infrastructure and the renewable energy industry.

Figure 2. The unique, patented Smart Cut process of Soitec, adapted to SiC material.

Our efforts at developing our Smart Cut technology have been driven by a team of engineers, working tirelessly at the Substrate Innovation Center of Grenoble, within CEA-Leti. Their success allows us to leverage: the exceptional physical characteristics of single-crystal SiC substrates, which are used as a donor and enable a ten times re-use capability; and an innovative, highly-electrically conductive polycrystalline substrate, acting as a handle wafer, that ensures a reduction in the device’s on-resistance.

We showcased our cutting-edge, high value-added engineered substrate technology last year, in issue VI of Compound Semiconductor. Here we go one step further, presenting the maturity of SmartSiC, the milestones towards its wide-scale adoption, and the steps we will take to drive further innovation.

Greener, faster, better
SmartSiC is a technology that is greener, faster and better in both its 150 mm and 200 mm formats. These strengths have put it on a trajectory to become one of the industry standards for the SiC market. It provides a plug-and-play solution that can seamlessly integrate into all existing power supply manufacturing lines and deliver significant commercial, environmental, and manufacturing benefits compared with traditional SiC substrates.

The greener footprint comes from the simple, energy-efficient manufacturing processes for making SmartSiC. Compared with traditional SiC, carbon dioxide emissions are reduced by up to 70 percent per wafer.

Faster deployment of these large size substrates stems from re-use of scarce, 200 mm single-crystal donors. By adopting this approach, we help to sustain market growth.

Our SmartSiC provides a better way to produce power electronics devices, by combining a superior manufacturing yield with better efficiency and a higher power density. Empowered by a higher conductivity compared with bulk SiC, SmartSiC enables an increase in current density of more than 20 percent for a range of power devices, including MOSFETs and diodes. This is the secret formula for unleashing a new generation of power devices.

We have two flavours of SmartSiC. One is SmartSiC-Performance, which is being prototyped and is moving through qualification trials with Soitec customers. The other, SmartSiC-Advanced, provides a substrate that is free from basal plane dislocations (BPDs). This product, now in the sampling phase, is being developed by our innovation team.

Employing an optimised design, our SmartSiC substrates feature a state-of-the-art single-crystal SiC layer that’s thinner than 1 µm, on top of an ultra-high-conductivity polycrystalline SiC handle substrate. These engineered substrates, with diameters of 150 mm or 200 mm, have a total thickness of 350 µm or 500 µm, respectively. When producing a second SmartSiC wafer, we re-use the donor wafer, minus the few microns used for the first SmartSiC wafer. By repeating this process again and again, we yield a minimum of ten SmartSiC wafers per donor wafer.

The production of polycrystalline SiC, which provides a handle wafer for each SmartSiC, uses a CVD process. This is quicker and more environment-friendly than PVT, needed for high-quality single-crystal SiC wafers. Our polycrystalline SiC that we source from external suppliers has adequate doping to control the substrate’s electrical conductivity while maintaining a highly competitive cost (see Figure 3).



Figure 3. Main process steps for manufacturing polycrystalline SiC.

Drawing on a high level of maturity and expertise developed over many years, we are able to define and ensure the perfect geometry for our engineered SiC substrate, key for mastering the bonding of the wafers. Our acquisition of NovaSiC in November 2021 has equipped us with more than 25 years of experience in SiC wafering, strengthening our capabilities.

We now have a highly capable, stable process and design for our SmartSiC substrates. These wafers have been tested and prototyped intensively and at large scale; and we have confirmed the value they bring to the market, to power devices and to power systems. Measurements of MOSFETs and diodes incorporating our SmartSiC engineered substrates show significant, irrefutable performance improvements, as well as enhanced long-term reliability and high-temperature robustness. These attributes have motivated several device manufacturers to commit significant resources to adopting and implementing SmartSiC technology when qualifying their next-generation products.

Glimpsing into the R&D kitchen
A target for our R&D team is to take the manufacturing yield of SiC to the globally accepted standards applied to silicon-based power devices. This ambitious goal is within reach, thanks to the capability of the Smart Cut process to maintain the crystal quality of the incoming donor wafer. According to inspection of our engineered wafers etched with a potassium hydroxide solution, as the decorated crystal defects we observed on the donor and SmartSiC surface are at the same locations, we know that our technology does not introduce additional imperfections. To verify this and improve the defectivity level, we have performed the Smart Cut process on a donor that is free from BPDs. Transferring a layer that is free from BPDs is behind our SmartSiC-Advanced substrates (see Table 1 for BPD density values for this class of engineered substrate).

One of the merits of having a BPD-free layer at the top of a SmartSiC-Advanced substrate is that it provides an excellent seed layer for drift epitaxy. This layer slashes the density of potential nucleation sites for killer defects, expands the epitaxy process window, and simplifies the epitaxial stack, which no longer needs a conversion buffer.

According to our simulations of yield and our experiments, the improvements that result from our BPD-free layer drive down the induced epi-grown killer-defect density by a factor of ten. The upshot is a hike in manufacturing yield of more than 20 percent for devices with areas of 20 mm² or more.

Removing BPDs also aids device reliability: it prevents dislocations from gliding and eliminates bipolar degradation. Insiders of the SiC industry expect the absence of BPDs to deliver a substantial improvement to the production process, with manufacturing yields expected to climb towards 90 percent.

Figure 4. Etching with potassium hydroxide enables crystal defect characterization. Decorations are easily visible with an optical microscope, allowing comparison between a single-crystal SiC donor (left) and SmartSiC (right).

Another asset of our SmartSiC, achieved through the high doping level of the polycrystalline SiC handle substrate, is the ease of forming a back-side ohmic contact for the SiC power device – either a MOSFET or a diode. Thanks to this, we recently demonstrated an annealing-free ohmic-contact process that can be easily implemented on SmartSiC substrates without compromising long-term die assembly reliability.

Table 1. Basal plane dislocations and defectivity density in the donor SmartSiC-Advanced substrate.

We have started to sample our SmartSiC-Advanced 150 mm engineered substrates. Prototypes are under evaluation by our key customers, and they are available to other customers on demand. At this year’s ICSCRM, to be held in Davos, Switzerland, in mid-September, we will present detailed data associated with our SmartSiC-Advanced technology, and deliver four papers.

Figure 5. Soitec’s new plant, Bernin 4, located in south-east France.

Ramping production
Our next step is, of course, high-volume production. Paving a path towards this goal, in March 2022 we broke ground at our new factory site, Bernin 4. It will be dedicated to the large-scale manufacture of SmartSiC, with production slated to begin in mid-2023 (see Figure 5). Equipped with this state-of-the-art infrastructure, we will ramp-up SmartSiC production in 2024 and beyond, to reach a total annual capacity of 150 mm and 200 mm wafers of 1 million by 2030.

Production will be dominated by 200 mm SmartSiC. Part of the motivation for majoring on this format is that our experience, over several decades, indicates the exponential benefits of increasing wafer size. When we supply the SiC industry with 200 mm SmartSiC wafers, manufactured with ten-times re-usability, we will make a massive difference to optimising the use of resources. We will relieve pressure in supply chains and enable efficient, accelerated production and adoption of our engineered substrates in automotive and industrial markets. We have already laid the groundwork for this revolution. Multiple partners have evaluated our SmartSiC-Performance prototypes (see Figure 6), and are impressed with them. Throughout this year we are enlarging and accelerating this qualification phase.

Figure 6. SmartSiC wafers in 150 mm and 200 mm formats.

Figure 7. The SmartSiC industrialization roadmap.

SmartSiC: A new industry standard
The electrification of the automobile is a once-in-a-century transformation that is generating a deluge of innovation. During the previous revolution in transportation, dating back to the early 1900s, it took 15 years for the world to switch from the horse-driven vehicle to mechanical mobility. Let’s hope that the transition from gasoline-powered vehicles to EVs will be far faster, given the urgent need to
cut carbon dioxide emissions and curb global warming.

We are already underway, as following in the footsteps of Tesla, many makers of EVs are now adopting SiC. Nevertheless, there are numerous hurdles to overcome, in terms of electrical performance, productivity, cost and yield, before SiC can take centre stage in the EV sector. We have anticipated these challenges and the upcoming demand from the EV industry, responding with the development of SmartSiC, a higher value-added alternative to the single-crystal SiC substrate. As our purpose statement says: ‘In our soil grows an amazing future.’

Bio: Pierre Barnabé appointed new CEO of Soitec
Pierre Barnabé took up the position of Chief Executive Officer of Soitec on 26 July, 2022, after joining Soitec in May 2022. Between 2015 and 2021, Barnabé was Executive Vice-President of the Atos group in charge of the Big Data & Cybersecurity (BDS) division. He also managed the group’s Public Services & Defense and Manufacturing activities and was interim group CEO in 2021. Before its acquisition by Atos in 2014, he was the Deputy CEO of Bull, the unique European leader in supercomputing, electronics for artificial intelligence, cybersecurity and cyberdefense from 2013 to 2015. From 2011 to 2013, he was Managing Director of the Enterprise branch of the French Telco SFR. Prior to this, he held various positions at Alcatel then Alcatel-Lucent.


The strengths of SmartSiC

Christophe Maleville is CTO and SEVP Innovation, Soitec

Christophe, your SmartSiC technology is relatively young compared with SiC technology. How would you describe the maturity of SmartSiC?

CM: Soitec’s SmartSiC technology is moving to the industrialization phase. We used our pilot line at CEA-Leti to develop, prototype and select a tool-of-record for high-volume manufacturing. We are now focusing on reducing variability, improving defectivity and yield, and optimizing the metrology sampling to start the high-volume manufacturing phase with an optimal process flow. We have 30 years of experience with Smart Cut in large volumes. Our advantage is that we can leverage this experience to now accelerate the maturation of our SmartSiC technology. And we are perfectly on time to get ready for manufacturing in 2023.

What level can you reach when considering product variability?

CM: Those who lead the development of SiC have done a fantastic job. They have introduced major improvements in SiC’s crystal quality and diameter, and SiC devices are now already routinely powering electric vehicles that are driving on our roads. But every SiC boule and every wafer within each boule is different, bringing quite a significant variability to manufacturing. SmartSiC is lowering such variability by allowing us to use each single wafer more than ten times, thanks to our Smart Cut process. By using an epitaxy layer as a donor, I strongly believe that our next generation of SiC wafers, SmartSiC, will completely eliminate crystal-originated variability. By eliminating basal plane dislocations prior to layer transfer, every wafer sent for device manufacturing will be the same. This will be a major benefit for large-volume production and will close the gap with silicon technologies.

Can Soitec lead this revolution alone?

CM: This is indeed a revolution that will lead to major advancements in SiC device performance and metrics. But, of course, we are not doing it alone. We are collaborating with strategic partners on all fronts, from research and technology organisations to materials and equipment suppliers and leading device manufacturers. This is absolutely fundamental to accelerate the adoption of SmartSiC-based devices and the implementation of next generations. For the manufacturing of our first generation of SmartSiC wafers, which will kick off in 2023, the development cycle was extremely rapid: we went from initial development work to a volume ramp-up in only four years. This clearly demonstrates how efficient our model of close collaboration within the ecosystem is.