Epitaxial transfer enhances electronic-photonic circuits

A scalable process that unites silicon with the III-Vs allows well-established electronic applications to be served alongside those requiring specialized photonics.

BY LEAH ESPENHAHN, JOHN CARLSON, PATRICK SU AND JOHN DALLESASSE FROM THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN

For many decades we have been dreaming of a new era for integrated circuits, where complex electronic functions are combined with dense photonic emitters on a single die – all accomplished at manufacturing scale. Up until now, the application of this vision has been hindered by the limited potential for broad deployment of such circuits. There has been no market pull for this technology, as well as insufficient motivation to drive development of viable integration processes, which are scalable and eliminate precision alignment at the individual emitter level.

Now, however, that need is finally arriving. The deployment of VCSEL arrays for facial recognition, general 3D imaging, and lidar has prompted the question: ‘How dense can we integrate these functions?’ There is also a related question, arising from the massive power requirements of data centres: ‘What is the lowest energy we can use to transmit all this information?’ For those that ponder both those questions for long enough, they’ll ultimately be mulling over this: ‘How do I combine dense electronic and photonic functions on a single die in a wafer-scale process?’

Many groups have wrestled with the later question. This has spawned many different approaches to integrate III-V material with silicon – and all have significant drawbacks. Take, for example, flip-chip bonding, a process that takes fully-formed VCSELs, or other photonic components, and attaches them to silicon die with solder or stud bumps. The placement accuracy of these flip-chipped devices is often limited by the capability of the pick-and-place tool, and the connection formed by the solder bumps tends to provide a poor thermal pathway restricting device performance. Another downside of this process is that it is slow, with any improvement in placement accuracy coming at the expense of throughput.

To alleviate these drawbacks, our team from the University of Illinois at Urbana-Champaign has developed an epitaxial transfer integration method that has many merits compared with alternative technologies. Its primary merits are: the opportunity to select different III-V epitaxial stacks for distinct photonic functions; the use of a wafer-scale photolithographic process to align photonic devices to electrical components; and an improved thermal pathway, enhancing heat extraction from the III-V photonic devices.

Our epitaxial transfer technique allows us to define selective III-V materials in specified regions on the silicon host, rather than integrating full wafers or fabricated die. With this approach we fabricate photonic devices with a wafer-scale process following the formation of these islands – this eliminates the need for individual high-precision die placements. Such a methodology has a level of functionality that allows emitter and detector epi to be integrated to provide optical input/output, and facilitates integration of a VCSEL dot projector with a CMOS imaging array, to provide a greater density of function in mobile handsets (see Figure 1 for an illustration of the functionality).

Figure 1. Depiction of an integrated CMOS die enabled by epitaxial transfer, including an integrated array of III-V photonic devices with silicon electronic circuitry.

Strengths of our approach include more efficient use of III-V material and a higher density of function, leading to circuits that are smaller, lighter, cheaper and consume less power. What’s more, unlike other integration methods, our technology allows designers to integrate different III-Vs across the wafer with unparalleled density, enabling them to take advantage of the broad range of functions made possible with distinct III-V semiconductors for different components and devices. And on top of that, our integration technique offers the improved alignment of photonic devices and the opportunity to increase their density.

Our two-step approach begins by using a carrier wafer to provide coarse alignment of the photonic device epitaxial material, a task that is well within the accuracy of pick-and-place machines and the alignment accuracy of low-precision bonding tools. The second step, which aligns the photonic devices relative to the features in the silicon wafer hosting the electronic devices, is performed after integration, using wafer-scale photolithographic process steps. This strategy enables us to make more compact and diverse devices than would be possible with standard integration techniques, which are limited in accuracy.

There are also gains that result from the removal of the III-V substrate during integration. Its extraction enables epitaxial material to take advantage of some of silicon’s material properties after bonding. The benefits are particularly impactful with the most used III-V substrate material, GaAs, which has a relatively poor thermal conductivity compared with silicon. As we shall see in due course, when GaAs-based photonic devices are integrated with silicon and the substrate then removed, they deliver an improved thermal performance relative to devices fabricated on a native GaAs substrate.

The process flow for creating our silicon-photonic circuits utilizes two silicon wafers; a host and carrier (an overview is provided in Figure 2). Fabrication begins by applying a standard front-end-of-line process to a silicon host, and using a second carrier wafer to prepare the III-V material for integration. Any number and variety of III-V chiplets are temporarily bonded to this carrier. A permanent bond is subsequently formed to the silicon wafer with electronic devices, following III-V substrate removal, photolithography and dry etching. The final step is the fabrication of photonic devices and arrays on the integrated III-V materials.

Figure 2. An overview of the silicon/III-V integration approach pursued at the University of Illinois at Urbana-Champaign.


Epitaxial transfer integration
Our integration process can be divided into three main stages: III-V substrate removal, III-V island formation, and epitaxial transfer (see Figure 3 for an illustration of these three steps).

During III-V substrate removal we temporarily bond pieces of III-V material to a silicon carrier. The bonding of these small pieces of III-V, which may be referred to as chiplets, is epitaxial side down. This process begins by depositing, onto the carrier wafer, a thin dielectric that serves two purposes: this layer improves adhesion to the temporary bonding polymer; and it reduces thermal stresses during the bonding processes, leading to superior process uniformity. Following the addition of the dielectric, a temporary bonding polymer is spun on top of this layer using a standard photoresist spinner. After that, chiplets are placed on the polymer, positioned in approximately mirrored locations to where the III-V epitaxy is desired on the final, silicon CMOS host. Note that in a manufacturing setting this process would be undertaken with a pick-and-place machine. The bonding polymer is then cured in a nitrogen-purged vacuum environment, with pressure applied to the top of these chiplets to minimise air pockets and contaminants that would degrade the bonding process. Following bonding of the chiplets to the silicon carrier, the III-V substrate is removed to leave just the III-V epitaxial layers bonded to the carrier. Lapping removes the substrate, creating material polished to a mirror finish. In our lab, we lap witha manual process that typically leaves 5 µm - 15 µm of III-V substrate. But this could be reduced significantly with industry-level lapping tools.

After substrate removal, chiplets are defined into III-V islands with a photolithographic process. This eliminates unneeded III-V material and provides precise definition of the islands locations. Determining the size of these islands is the accuracy of the wafer-to-wafer bond alignment tool, as well as the intended size for the photonic devices. Using standard methods we metallize the islands, in preparation for their eutectic bonding to pads on the silicon host wafer.

Following carrier wafer processing, our metallized III-V islands on the carrier wafer are brought into contact with metal pads on the silicon host wafer, before the stack is placed in a conventional wafer bonding tool. A eutectic alloy is formed between the metals, allowing a permanent bond to form at low, CMOS-compatible temperatures. Once the eutectic bond is fully formed, the carrier wafer and remaining temporary bonding polymer are removed, to leave only the transferred epitaxial material on the silicon host substrate. The III-V material is planarized using a planarization polymer, in this case BCB-3022, before it is processed into photonic devices.

VCSEL Integration
From facial recognition in smartphones to autonomous vehicle object detection and data communication, VCSELs serve ubiquitously in modern consumer and enterprise applications. Yet despite all this success they have their weaknesses. One major concern is a device performance that plummets under high-temperature, compounded by a poor thermal conductivity of the GaAs substrate. Another issue is an emission wavelength that shifts with temperature, creating challenges for some elements that may be in the optical path, such as diffractive optics, gratings, and filters.

To combat these concerns, we are pioneering integration of VCSELs via epitaxial transfer from GaAs to silicon. This new foundation alleviates heating effects in VCSELs, resulting in improved efficiencies and wavelength stability, even at elevated temperatures.

Figure 3. III-V epitaxy integration on silicon process flow (not to-scale).

We have demonstrated the benefits of this approach by forming a permanent bond for the VCSEL epitaxial islands with a Pd/Ge stack, which is a standard gold-free n-contact for GaAs-based devices. We metallize the silicon host with a
Ti/Al stack, chosen because titanium improves adhesion and aluminium forms a eutectic alloy with germanium on the epitaxial islands. The Ti/Al stack provides an n-side contact for the VCSELs, where a probe area for testing is available via exposed metal between these devices (see Figure 5 (a)).

The VCSELs we fabricate on integrated epitaxial material have a standard device structure, a 10 µm-diameter oxide aperture, and a standard Ti/Pt/Au stack for the p-contact (see Figure 4). Gold, commonly used as a protective metal cap layer, fulfils that role in these VCSELs. However, it could be replaced by a different metal to maintain CMOS compatibility for fully integrated devices.

Figure 4. The integrated VCSEL pioneered by the team from the University of Illinois at Urbana-Champaign benefits from removal of the GaAs substrate.

To evaluate the thermal performance of our integrated devices, we tested them from room temperature (23 ˚C) to 50 ˚C, using a thermoelectric cooler operating under reverse bias to adjust the temperature of the devices. Tracking the temperature was a temperature probe, while wafer probes provided current injection and measured the voltage outputs. To measure the VCSEL’s optical output, above this device we placed a ball-lensed optical fibre probe, connected to a Newport 818-UV photodetector with an OD-3 attenuator. Our measurements showed that our VCSELs are capable of CW operation at room temperature, with a threshold current of approximately 4 mA and a rollover at 33 mA.

Our value for the threshold current is common for non-optimized VCSELs of the given oxide aperture size, but the thermal rollover occurs at a much higher current than usual, indicating an improved thermal environment for the device.
At the elevated temperature of 50 ˚C, the threshold current increased to approximately 6 mA and the rollover decreased to 29 mA. These shifts from room-temperature values are consistent with the whole device heating to the set temperature.
Differential resistance for our VCSEL is 37 Ω at room temperature and 33 Ω at 50 ˚C. These values are relatively low, thanks to removal of the thick GaAs substrate from the current path.

Another benefit that stems from the improved thermal environment of our VCSELs is the quashing of the temperature-induced wavelength shift with current injection. Measurements of VCSEL emission spectra – recorded by positioning an optical fibre, connected to an optical spectrum analyser, above the centre of the device – revealed that compared with a non-integrated device of similar aperture size, our variant produces a three-fold decrease in red-shift with current (see Figure 5 (c) and (d)). In comparison to flip-chip bonded VCSELs with a similar aperture size, our VCSEL bonded via epitaxial transfer has around a seven-fold decrease in red-shift, according to reports in the literature. These results highlight the significantly enhanced wavelength stability of integrated VCSELs produced by the epitaxial transfer integration technique compared with their state-of-the-art standalone siblings.

Figure 5. Integrated VCSEL results. (a) Scanning electron microscopy of VCSELs. Left: 10 µm oxide aperture VCSEL, right: unused, 20 µm oxide aperture VCSEL. (b) Light-current-voltage (L-I-V) measurements of VCSEL from room temperature (23 ˚C) to 50 ˚C. (c) Optical spectra of a VCSEL from room temperature (23 ˚C) to 50 ˚C, for drive currents from 5 mA to 20 mA. (d) Comparison of normalized leading peak wavelength shift between an integrated VCSEL and a non-integrated VCSEL of similar oxide aperture size.

Our work highlights the primary strengths of our process: it’s wafer scale, and its capability to form photonic devices on silicon with precise referencing to features on the silicon host. We are encouraged that our results do not just show parity of performance for our VCSEL, but improved performance. This highlights the potential of this process for large-scale electronic-photonic integration. The possibilities, including highly compact systems for 3D imaging and data transmission, are endless.

This feature draws upon work supported by the National Science Foundation under Grant No. (1640196). The authors are additionally thankful for support provided by the II-VI Foundation. Figure 5 (a), (c), and (d) are variations
upon figures first presented in Espenhahn, 2022 cited below in “Further Reading”.

Further reading
† J. Dallesasse et al. “Heterogeneous Integration for Silicon Photonic Systems: Challenges and Approaches.” 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2021.
† L. Espenhahn et al. “Heterogeneously integrated VCSELs on silicon.” Vertical-Cavity Surface-Emitting Lasers XXVI. 12020 SPIE (2022)
† J. Carlson et. al. “Multi-chip heterogeneously integrated array of active three-terminal transistor lasers and passive photonic structures for electronic-photonic integration on silicon.” Silicon Photonics XV 11285 International Society for Optics and Photonics (2020)