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Technical Insight

Magazine Feature
This article was originally featured in the edition:
Volume 28 Issue 8

Epitaxial transfer enhances electronic-photonic circuits

News

A scalable process that unites silicon with the III-Vs allows well-established electronic applications to be served alongside those requiring specialized photonics.

BY LEAH ESPENHAHN, JOHN CARLSON, PATRICK SU AND JOHN DALLESASSE FROM THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN

For many decades we have been dreaming of a new era for integrated circuits, where complex electronic functions are combined with dense photonic emitters on a single die – all accomplished at manufacturing scale. Up until now, the application of this vision has been hindered by the limited potential for broad deployment of such circuits. There has been no market pull for this technology, as well as insufficient motivation to drive development of viable integration processes, which are scalable and eliminate precision alignment at the individual emitter level.

Now, however, that need is finally arriving. The deployment of VCSEL arrays for facial recognition, general 3D imaging, and lidar has prompted the question: ‘How dense can we integrate these functions?’ There is also a related question, arising from the massive power requirements of data centres: ‘What is the lowest energy we can use to transmit all this information?’ For those that ponder both those questions for long enough, they’ll ultimately be mulling over this: ‘How do I combine dense electronic and photonic functions on a single die in a wafer-scale process?’

Many groups have wrestled with the later question. This has spawned many different approaches to integrate III-V material with silicon – and all have significant drawbacks. Take, for example, flip-chip bonding, a process that takes fully-formed VCSELs, or other photonic components, and attaches them to silicon die with solder or stud bumps. The placement accuracy of these flip-chipped devices is often limited by the capability of the pick-and-place tool, and the connection formed by the solder bumps tends to provide a poor thermal pathway restricting device performance. Another downside of this process is that it is slow, with any improvement in placement accuracy coming at the expense of throughput.

To alleviate these drawbacks, our team from the University of Illinois at Urbana-Champaign has developed an epitaxial transfer integration method that has many merits compared with alternative technologies. Its primary merits are: the opportunity to select different III-V epitaxial stacks for distinct photonic functions; the use of a wafer-scale photolithographic process to align photonic devices to electrical components; and an improved thermal pathway, enhancing heat extraction from the III-V photonic devices.

Our epitaxial transfer technique allows us to define selective III-V materials in specified regions on the silicon host, rather than integrating full wafers or fabricated die. With this approach we fabricate photonic devices with a wafer-scale process following the formation of these islands – this eliminates the need for individual high-precision die placements. Such a methodology has a level of functionality that allows emitter and detector epi to be integrated to provide optical input/output, and facilitates integration of a VCSEL dot projector with a CMOS imaging array, to provide a greater density of function in mobile handsets (see Figure 1 for an illustration of the functionality).