Enhancing the ferroelectric gate HEMT
Adding lanthanum doping and a ZrO2 seed layer to a normally-off
ferroelectric gate HEMT causes leakage currents to fall, threshold
voltage stability to increase and lifetime to lengthen.
BY EDWARD YI CHANG FROM NATIONAL YANG MING CHIAO TUNG UNIVERSITY
GaN is an incredible material for producing high-power and high-frequency electronic devices. In particular, when it is used to make a HEMT, it enables exceptional performance in power switching and radio-frequency applications. Drawing on the unique polarisation-induced electric field, the GaN HEMT combines a very low resistance with a high output power. However, the internal electric field within this device is both a blessing and a curse, as it creates an obstacle to enabling
enhancement-mode operation, which is strongly desired for safe operation in power-switching systems.
Given the importance of realising enhancement-mode operation, also known as normally-off, it’s not surprising that several technologies have been developed to meet that goal. Those approaches include the introduction of a recessed gate, p-GaN gate, fluorine implantation, and oxide charge engineering. For all these designs, to avoid faulty turn-on, the threshold voltage for a power device should be around +3 V. However, meeting this requirement and ensuring normally-off operation has compromised performance, with the approaches just described for realising enhancement mode leading to an inferior current density and on-resistance, compared with state-of-the-art normally-on devices. So the search has continued for a normally-off GaN technology for power devices.
Figure 1. An enhancement-mode hybrid ferroelectric GaN HEMT with a charge storage gate combines a high threshold voltage with a low on-resistance and a high output current.
Offering much hope in this regard is the work of our team at the National Yang Ming Chiao Tung University, Taiwan. Recently, we have developed ferroelectric charge trapping gate (FEG) GaN MIS-HEMTs, namely FEG-HEMTs.
These hybrid, novel, high-performance devices combine good power-electronic characteristics with those associated with flash memory. Drawing on the low crystallisation temperature for solid solutions of Hf0.5Zr0.5O2 and the feasibility of atomic layer deposition, the hybrid ferroelectric charge-trapping gate stack that lies at the heart of our devices has gradually gained a great deal of attention, because it enables a simple way to realise enhancement-mode operation with a threshold voltage of more than 2.5 V. The combination of the charge-trapping layer and the ferroelectric leads to a positive shift in the threshold voltage beyond the safety margin of +2.5 V after a positive gate bias initialisation. This ensures enhancement-mode operation (see Figure 2).