Scaling III-V technologies for 5G and 6G

Upscaling GaN HEMTs and InP HBTs to a silicon platform and in co-integrating them with CMOS components fulfils the requirements for next-generation high-capacity wireless communication.

BY NADINE COLLAERT FROM IMEC

As every year goes by, yet more data is transmitted wirelessly, driven by an ever-growing group of users. To enable this trend to continue, while making data transfer faster and more efficient, owners of mobile networks are now rolling out the fifth generation of wireless technology infrastructure – and they are already starting to consider what lies after.

Today’s 5G networks are capable of peak data rates of 10 Gbit/s. When 6G follows – its deployment is slated to commence in 2030 – rates as high as 100 Gbit/s are expected. To ensure that this will be a success, researchers have much to consider. As well as figuring out how to accommodate more data and connections, efforts must be directed at investigating how the next generation of wireless communication will support new use cases, such as autonomous driving and holographic presence.

To enable exceptional data rates, the telecom industry has already been shifting wireless signals to higher frequencies. While 5G initially employed sub-6 GHz frequency bands, products targeting 28/39 GHz have been showcased. There is also growing interest in FR3 frequency bands within the 6-20 GHz domain for 5G networks, as they offer a great balance between coverage and capacity. For 6G, frequencies above 100 GHz are now being discussed.

Figure 1. Comparing the power consumption of CMOS, SiGe, and InP devices in transmitter architectures as a function of the number of antennas (as presented at IEDM 2022).

There is much to be gained with a move to higher frequencies. One of the most significant benefits is the introduction of new frequency bands, thereby addressing the spectrum scarcity issue within existing bands. Another advantage is that the higher the operating frequency, the easier it is to obtain a wider bandwidth. In addition to these merits, a combination of frequencies above 100 GHz and bandwidths up to 30 GHz allow telecom operators to, in principle, use lower-order modulation schemes within wireless data links. In turn, this trims power consumption.

Higher frequencies also deliver benefits coming from shorter wavelengths. As the antenna array size scales with the square of the wavelength, higher frequencies allow antenna arrays to be packed far more densely. This contributes to better beamforming, a technique that ensures that a greater proportion of transmitted energy arrives at the intended receiver.

Moving to higher frequencies is not without challenges. Today, CMOS is the preferred technology for building the critical components of transmitters and receivers, including the power amplifiers within the front-end modules that send radio-frequency signals to and from the antennas. As the operating frequency increases, CMOS-based power amplifiers struggle to deliver the required output power with a sufficiently high efficiency.

This is where technologies such as GaN and InP come into play. Thanks to their outstanding material properties, these III-Vs stand a far better chance of providing the required output power and efficiency at high operating frequencies. For example, GaN combines a high current density with a high electron mobility and a large breakdown voltage. The high power density also enables a small form factor, and thus a trimming of the overall system size while maintaining performance.

Figure 2. Output power for 28 GHz and 39 GHz operating frequencies in (left) fixed wireless access (FWA) and (right) user equipment: a comparison of three different technologies (as presented at IEDM 2022).

Outclassing CMOS
At imec, the internationally renowned microelectronics centre, we have been considering the opportunities for III-V technologies in tomorrow’s wireless infrastructure, and the device architectures best suited for this advance. Our efforts have included a modelling exercise, where we have compared the performance of three different power amplifier implementations operating at 140 GHz: entirely CMOS; a CMOS beamformer, in combination with a SiGe HBT; and an InP HBT. The latter emerged as the clear winner, in terms of both the output power (over 20 dBm) and energy efficiency (20 to 30 percent). It’s worth noting that our modelling also revealed that for InP, the optimal point for energy efficiency is obtained with relatively few antennas. This is a significant asset when real estate is at a premium, which is the case in mobile devices.

Additional modelling by our team shows that at lower millimetre-wave frequencies it is GaN that exhibits excellent performance. At both 28 GHz and 39 GHz, GaN-on-SiC HEMTs outclass CMOS-based devices and GaAs HEMTs, in terms of output power and energy efficiency. The superiority of GaN is seen in two different use cases: fixed wireless access, with 16 antennas; and user equipment, with four antennas.

The Achilles heel for III-V devices is the cost and complexity of integration – GaN and InP device technologies are not yet able to fully compete with CMOS-based technologies. III-V devices tend to be produced on small and costly non-silicon substrates, and rely on less suitable processes for high-volume manufacturing.

An exciting way forward is to integrate III-V devices on 200 mm or 300 mm silicon wafers. This approach promises overall optimisation while maintaining superior RF performance. As well as being much cheaper, silicon substrates open the door to CMOS-compatible processing that enables large-scale manufacturability.

Figure 3. GaN-on-silicon benchmarking data. The imec data in red is among the best reported for GaN-on-silicon devices and comparable to GaN-on-SiC substrates (as presented at IEDM 2022). References: [1] H.W. Then et al. IEDM 2020; [2] H.W. Then et al. IEDM 2021; [3] W. Wang et al. J-EDS 2018; [4] Y.C. Lin et al. Micromachines 2020; [5] M. Mi et al. TED 2017; [6] Y. Zhang et al. EDL 2018; [7] K. Harrouche et al. HAL open science, 2020; [8] J.-S. Moon et al. MTTS 2019.

Integrating GaN and InP on a silicon platform is far from trivial. It demands new approaches for transistor and circuit design, new materials, and different manufacturing techniques. One of the main challenges relates to the large lattice mismatches of the III-Vs with silicon: 8 percent for InP and 17 percent for GaN. These significant differences threaten to create many defects in the layers and ultimately degrade device performance.

Another challenge is to co-integrate the components that are based on either GaN-on-silicon or InP-on-silicon with CMOS-based components and create a complete system. Initially, GaN and InP technologies will be used to realise the power amplifiers within the front-end modules. However, there is also the possibility to improve the performance of low-noise amplifiers and switches by drawing on the unique properties of these compound semiconductors. But in the end, CMOS will still be needed for calibration, control, and beamforming.

Through our Advanced RF Program that includes contributions from industry partners, we have been exploring various ways to integrate GaN and InP devices on large-size silicon wafers, and how to enable their heterogeneous integration with CMOS components. This work has included an assessment of the pros and cons for different use cases – infrastructure, such as fixed wireless access, as well as user equipment.

Figure 4. Schematic representation of the different InP-on-silicon growth approaches: (a) nano-ridge engineering; (b) blanket growth with strain relaxed buffers, and (c) wafer reconstruction.

Improving RF GaN-on-silicon
Variations in the starting substrate give rise to several flavours of GaN technology: GaN on native bulk substrates, GaN-on-SiC, and GaN-on-silicon. Of the three, today GaN-on-SiC is the most widely explored and already used for infrastructure applications, including 5G base stations. SiC substrates are more cost-efficient than bulk GaN technology, and SiC is an excellent thermal conductor – this aids heat dissipation in high-power infrastructure applications. However, SiC substrates are higher in cost than silicon and limited in size, making them less suitable for mass production.

In contrast, GaN-on-silicon has the potential to be upscaled to 200 mm and even 300 mm wafers. Thanks to years of innovation in power electronics, tremendous progress has already been made in the integration of GaN on large-size silicon substrates. However, additional improvement is needed to ensure that GaN-on-silicon technology is suitable for optimal RF performance. The main challenges are to deliver a comparable large signal and reliability performance to that of GaN-on-SiC, and to realise a higher operating frequency. Meeting these objectives requires: further innovation in material stack design and choice of materials; a reduction in the gate length of the HEMT; suppression of parasitics; and keeping RF dispersion as low as possible.

The GaN-on-silicon process flow for making RF devices at imec begins by loading 200 mm silicon substrates into an MOCVD reactor. Epitaxial growth follows, creating a structure comprising a proprietary GaN/AlGaN buffer, a GaN channel, an AlN spacer, and an AlGaN barrier. From this epiwafer we process GaN HEMTs with TiN Schottky metal gates that are subsequently integrated with a (low-temperature) 3-level copper back-end-of-line process.

We have recently realised competitive results with our GaN-on-silicon platform. Our success has brought the output power and power-added efficiency of GaN-on-silicon closer to that of GaN-on-SiC technology. Note that the power-added efficiency is a commonly used metric for evaluating the efficiency of a power amplifier, because it considers the effect of the amplifier’s gain on its overall efficiency.

Our combination of technology development and modelling will ultimately help to achieve even better performance and reliability for the GaN-on-silicon HEMT. At the most recent IEDM, held last December, we unveiled a simulation framework for improving predictions of thermal transport in RF devices. These simulations revealed that the rise in peak temperature is three times higher than predicted previously. The insight provided by this modelling offers further guidance for optimising RF devices and their layouts early in the development phase.

Figure 5. A 2-inch InP wafer, and a 300 mm silicon wafer with a InP nano-ride engineered HBT stack.

InP-on-silicon for 6G
For higher frequencies, InP HBTs are superior to GaN HEMTs, offering a better trade-off of output power and efficiency. This technology is also well understood, with researchers knowing how to design InP HBTs for optimal RF performance. However, fabrication tends to involve InP substrates with diameters below 150 mm, and lab-like processes that are not CMOS-compatible.

Within the research community there are three approaches under consideration for upscaling. Two rely on direct growth of InP on silicon and a third is based on wafer reconstruction. All three have the potential to provide a more cost-effective approach to production than current technologies, which use small InP substrates. There are pros and cons for all three approaches, in terms of performance, cost, and heterogeneous integration potential. We have assessed the benefits and challenges of all of them for various use cases – infrastructure as well as mobile devices.

One approach that many groups pursue for making InP HBTs on silicon is to bridge the 8 percent lattice mismatch with strain-relaxed buffer layers (see Figure 4(b)). InP is grown directly on top of this buffer. The opportunity to use larger wafer sizes, particularly in cases where some of the silicon could be reused, offers a significant cost advantage. However, this approach is challenging, with optimisation needed to drive down the defect density.

We depart from this ‘blanket’ growth approach, proposing nano-ridge engineering, an alternative technology that deals with defects more efficiently (see Figure 4 (a)). Nano-ridge engineering involves selective growth of III-V material in pre-patterned trenches, formed in a silicon substrate. These high-aspect-ratio trenches are incredibly effective at trapping defects –imperfections are only present in the narrow bottom part of the trench – thereby enabling the growth of high-quality, low-defectivity material out of the trench. Through overgrowth the nano-ridge widens towards the top, creating a solid base for a device stack. Our insights from a GaAs/InGaP case study are guiding our optimisation of the target InGaAs/InP nano-ridge engineered HBT devices.

Figure 6. Zoom-in of the 300 mm silicon wafer showing the dies with the InP nano-ride engineered HBT structures.

An alternative to direct growth is to place InP on silicon with a wafer reconstruction technology (see Figure 4 (c)). In this case, high-quality InP substrates – with or without active layers – are diced into tiles during wafer constitution. The tiles are then attached to a silicon wafer with die-to-wafer bonding. With this approach, the key challenges are associated with the efficient transfer of materials and the removal of the remaining InP substrate. Several techniques are being considered.

Towards heterogeneous integration
Ultimately, the III-V-on-silicon power amplifiers have to be combined with CMOS-based components that take care of the likes of calibration and control. We are evaluating various heterogeneous integration options, weighing their pros and cons for a number of use cases. The most common way to integrate different RF components in a system-in-package is to use an advanced laminate substrate technology. We are optimising this to make it more suitable for higher frequencies. On top of this, we are exploring more advanced options for heterogeneous integration, including 2.5D interposer and 3D integration technologies.

Note that for frequencies beyond 100 GHz, the antenna module starts to define the area that’s available for the transceiver. At such high frequencies, the antenna is smaller than the front-end module, which hardly scales in size with increasing frequency. When this is the case, one interesting option for configurations with a large antenna array is to shift the location of the RF front-end module to under the array. This is where 3D integration technologies – either die-to-wafer or wafer-to-wafer – come into play. They enable short, well-defined connections between the front-end module and the antenna modules. As great a concern for 3D integration is thermal management, which will be crucial to provide effective heatsinks. We are currently undertaking a comprehensive system-technology-co-optimisation analysis to evaluate a range of technologies for 3D integration and to guide technology choices from a system-level perspective.

For handheld devices, where a reduced number of antennas relax constraints, an interesting approach is 2.5D interposer technology. This option for heterogeneous integration, using a layer stack with lithography-defined connections, can accommodate through-silicon vias that enable communication between the III-V and the CMOS-based components. In this situation, the III-V devices sit next to the CMOS chip, ensuring superior thermal management, because both chips can be in direct contact with a heat sink. The downside of this architecture is that it only allows for 1D beam steering.

Figure 7. Schematic representation of an RF silicon interposer with integrated InP and CMOS devices and antenna array in a package.

Today we are evaluating hardware implementations of 2.5D interposer technology, looking into the most optimal combinations of substrates, dielectrics, and redistribution layers to minimise losses. Our successes on this front include a first version of an RF-tailored silicon interposer technology, using a standard silicon substrate, a copper semi-additive interconnect, and thick spin-on low-κ dielectrics that exhibit very low interconnect loss, even above 100 GHz.

Our recent upscaling and integration efforts are producing very promising results. We have shown that GaN-on-silicon and InP-on-silicon are set to become viable technologies for next-generation high-capacity wireless communication applications.

Further reading
• ‘Thermal modeling of GaN & InP RF devices with intrinsic account for nanoscale transport effects,’ B. Vermeersch et al., 2022 International Electron Devices Meeting (IEDM)
• ‘III-V/III-N technologies for next-generation high-capacity wireless communication,’ N. Collaert et el., 2022 International Electron Devices Meeting,