Loading...
News Article

Japanese team makes JFET that operates at 600degC

News
Bottom-gate design harnesses the intrinsic properties of SiC

A team of researchers at Kyoto University has looked afresh at using SiC in extreme environments, with a focus on SiC JFETs.

Previous research has suggested that complementary JFETs, based on SiC JFETs, can be applied to low-power integrated circuits for operation in extreme environments. However, the JFETs created previously -- which had conventional top-gate structures fabricated in semi-insulating SiC substrates -- suffered from low controllability and large leakage currents at high temperatures.

"Our goal is to open a new path forward with complementary JFETs designed to harness the intrinsic properties of SiC itself," said first author Mitsuaki Kaneko.

Rather than developing everything from scratch, the team deliberately employed industry-standard manufacturing methods to build their new JFET structure, adopting a bottom-gate design to improve the threshold voltage controllability. They also employed well-based isolation instead of a semi-insulating substrate to suppress the high-temperature leakage current.

The result was a new SiC transistor structure that succeeded on the very first attempt. Upon completion of the new design, the team was able to demonstrate that their device can operate successfully at 600°C. The adoption of the bottom-gate structure significantly improved the transistor's threshold voltage controllability and drastically reduced the leakage current, which is now very close to the theoretical limit predicted from the material properties of SiC.

The team's paper 'Over 600°C operation of ion-implantation-based SiC bottom-gate JFETs' in APL Electronic Devices shows that SiC is already a mature power device technology in itself, and demonstrates the immense potential of the newly developed bottom-gate structure for implementing reliable, extreme-temperature SiC-based integrated circuits.

However, many challenges still lie ahead on the path to practical implementation. One by one, the team intends to address these by creating more complex circuits, scaling up to wafer-level production, and ensuring the entire package remains robust in extreme environments.

Logo
x