Technical Insight
Targeting millimetre-wave communications with InGaAs HEMTs and silicon CMOS
Wafer level integration of InGaAs HEMTs and silicon CMOS can create millimetre-wave circuits with a small footprint, low cost and high performance by Sachin Yadav, Sang Xuan Nguyen, Fayyaz Singaporewala, Kenneth Lee, Eugene Fitzgerald and Xiao Gong from the Singapore-MIT Alliance for research and technology "“ low energy electronic systems
- Since the introduction of the integrated circuit in 1959, silicon has dominated the semiconductor industry. In the form of silicon CMOS, it has advanced at a rapid pace to offer an unparalleled device integration density.
However, silicon cannot do everything. In the highfrequency domain, devices made from this material are inferior to those formed from the likes of GaAs, GaN and InP "“ all those alternatives offer higher powers, lower noise and superior linearity. Due to this, the trend in modern communication devices is to bring together high-speed III-V devices and high-density silicon-CMOS on the same circuit board.
Until recently, this integration has taken place at either the board or the packaging level. That's not ideal, though, as it leads to a large circuit footprint, large interconnect losses, and high cost.
A far better option is wafer-level integration of different material systems. This approach opens up a plethora of new opportunities for future communication devices. As can be the case for a silicon-only RF technology, monolithic heterogeneous integration promises lower costs, reduced interconnect power consumption, superior circuit performance, a smaller chip footprint, fewer packages at the board level, and more room for circuit innovation for millimetre-wave communication applications, such as 5G mobile and wireless.
The superior performance that comes from monolithic integration partially results from the opportunity to position silicon and III-V devices very close together "“ they can be separated by a few microns, and sometimes even less. Systems that can be realized in this manner include a transceiver based on the hybrid monolithic integration of silicon and III-Vs (see Figure 1). This system can combine an RF front-end formed with high-performance III-Vs, or a combination of III-V and silicon-CMOS devices; with a digital baseband in highly integrated silicon-CMOS technology. It's a marriage that brings out the best in both III-V and silicon.
Figure 1. Hybrid transceiver systems can exploit the advantages of III-V and silicon-CMOS technologies. Using this approach, high-performance amplifiers, filters, and converters can be designed using III-V technologies, while the control and digital circuitry can be designed using silicon-CMOS. In addition, hybrid sub-circuits, such as ADC (analogue-to-digital converters) and DAC (digital-to-analogue converters), can be implemented using a combination of III-V and silicon-CMOS devices.
Which III-V?
Several III-V technologies can be used to produce power and low-noise solid-state amplifier technologies at millimetre-wave frequencies "“ that is, those that span 30 GHz to 300 GHz. Out of these options, InGaAs HEMTs and HBTs offer the most balanced noise and power performance for 5G applications (see Figure 2(a) for on-chip output powers of various microwave, millimetre-wave, and sub-millimetre-wave power amplifiers).
Figure 2. (a) Plotting the output power as a function of frequency for various on-chip III-V power amplifiers reveals that for operating frequencies less than 100 GHz, GaN-based power amplifiers provide a superior performance compared with that of other solid-state technologies. For frequencies above 100 GHz, InGaAs HEMTs and InP HBTs lead to the best power performance. (b) Comparing noise figures at various frequencies for various low-noise amplifiers shows that those based on InGaAs HEMTs provide the best noise performance.
The preference for InGaAs might raise a few eyebrows, given the success of GaN in the RF domain. However, while GaN-based MMICs exhibit the best power output among the solid-state device technologies, the GaN PA is compromised by a high operating voltage, due to the large knee-voltage of the GaN HEMT.
If a hybrid III-V and silicon technology is to create a device with tremendous sales, it will have to target a high-volume product that already uses silicon. In the wireless space, such volumes are already achieved in mobile devices, such as handsets. Handsets, however, operate at voltage ranges where GaN loses its primary advantage.
For frequencies exceeding 100 GHz, the best PA performances come from InGaAs HEMTs and InP HBTs. Of these two, InGaAs HEMTs have lower noise figures, making them the premier choice for low-noise amplifiers operating in this frequency domain. The upper hand stems from the record high transconductance, electron mobility, and cut-off frequencies of InGaAs HEMTs "“ and bandgap engineering enables these devices to span a frequency range that extends all the way from a few gigahertz up to 1 THz. So these devices are versatile, while their combination of medium output powers and low noise figures make the InGaAs HEMT-based amplifier the most suitable candidate for applications such as 5G mobile.
Integrating InGaAs and silicon
At the Singapore-MIT Alliance for Research and Technology Low Energy Electronic Systems (SMART-LEES) we are integrating InGaAs MOS-HEMTs with silicon CMOS, using 200 mm silicon wafers (see Figure 3).
One of the merits of this approach is that by using large-diameter wafers, we can address the ever increasing demand for such technologies. Additional attributes are that the integration can employ existing, mature silicon multi-layer interconnects; and hybrid circuits can be formed, by combining p-type silicon transistors with n-type InGaAs transistors. The separation between these two different types of devices may be as small as just a few microns.
The MOS HEMT is a lesser known device than the commercially available Schottky-gate HEMT. But in our circuits, we believe it's a better choice. In recent years, InGaAs MOS devices and ohmic contacts have received significant attention in the research community, due to successes that include a record transconductance for InGaAs quantum-well MOSFETs among all III-V FETs. Another feature of the MOS HEMT is that it can contain a high-κ gate oxide, which can slash the gate leakage current compared with that of the Schottky gate HEMT. This is most welcome, because it opens the door to more aggressive device scaling and higher device density.
We process our silicon CMOS and InGaAs front-end devices sequentially in a CMOS-flow (see "Uniting CMOS and InGaAs front-end devices"). Our process includes a wafer bonding step (see Figure 4).
Figure 4. (a) Photograph showing the bonded patterned SOI and InGaAson-silicon substrates. (b) A cross-sectional transmission electron microscopy image of the bonded SOI (patterned) and InGaAson-silicon substrates.
A key advantage of our approach is that it allows a decoupling of thermal budgets that are associated with front-end-of-line processes for silicon and InGaAs. Thanks to this, the high temperatures of 600 °C or more, which are needed for the epitaxial growth of the III-V device layers, are kept away from the devices formed on the silicon wafer during front-end-of-line processing. What's more, our approach avoids degradation that could be caused by exposing the InGaAs MOS-HEMTs to temperatures associated with the front-end-of-line processing steps used for silicon CMOS.
Growth of our InGaAs HEMTs is carried out in an Aixtron Crius MOCVD reactor, using 725 μm-thick silicon (001) substrates with a 6° offcut and a diameter of 200 mm. To balance the device cut-off frequency, which is related to electron mobility, with the breakdown voltage that is related to the energy bandgap, we use an indium composition in our channel of 30 percent. Buffer layers address the large lattice mismatch between In0.30Ga0.70As and silicon "“ it is 6.3 percent (see Figure 5 for details of the epistructure of our HEMT).
Figure 5. At SMART-LEES, InGaAs HEMT structures are grown on 200 mm silicon substrates using an Aixtron Crius MOCVD reactor.
To realise high-quality device layers, we have improved the material uniformity of our epitaxial structures, while decreasing the threading dislocation density, wafer bow and surface roughness. Using a high growth temperature of 630 °C and a relatively thick InAlAs graded buffer "“ it is about 1.5 μmthick "“ we have produced material with a threading dislocation density of 1±0.3 à— 107 cm-2, according to plane-view transmission electron microscopy. Based on results of 50 growth runs, wafers are slightly concave, with a bow of just 39±4 μm. Variations in material composition across the wafer are very small, thanks to a difference in temperature of just 5 °C from the centre of the wafer to its edge, and uniform gas flows provided by the showerhead configuration of the MOCVD tool.
Uniting CMOS and InGaAs front-end devices
Using the integration approach adopted by the engineers working in the Low Energy Electronic Systems group at Singapore, CMOS and InGaAs front-end devices are processed sequentially in a CMOS-flow. Fabrication involves the following steps:
Front-end-of-line processing of silicon CMOS
Growth, by MOCVD, of InGaAs HEMT epitaxial layers on a separate silicon wafer
Transfer of the front-end processed silicon CMOS layer to the InGaAs HEMT wafer using a multi-step process, which involves: bonding a front-end processed silicon-CMOS wafer (on SOI) to a silicon handle wafer; removing the silicon substrate from the silicon-CMOS wafer; bonding the resulting wafer to a InGaAs-on-silicon wafer; and removing the silicon handle wafer
Fabrication of InGaAs MOS-HEMTs in III-V windows using a siliconfoundry-compatible process. This involves refractory metal contacts and a lift-off free process
Forming interconnects between the silicon-CMOS and III-V devices with a back-end-of-line process
Atomic force microscopy reveals a root-mean-square surface roughness for the top n+-InGaAs cap layer of 5.7 nm (see Figure 6). Note that this value is higher than that for MBE-grown HEMTs, due to the higher growth temperature, which trades a superior material quality for a slight increase in cross-hatch roughness over large length scales.
Figure 6. (a) Atomic force microscopy scan of the top InGaAs surface for a scan area of 30 μm by 30 μm. The RMS roughness is about 5.7 nm. (b) Hall mobility data from various samples with different δ-doping species and indium compositions in the InxGa1-xAs channel. By optimizing the δ-doping, a μHall of more than 5000 cm2 V-1 s-1 can be realised in both tellurium and silicon δ-doped samples.
By varying the δ-doping concentrations and species, we realise mobilities in the In0.30Ga0.70As channel of 5000-6500 cm2 V-1 s-1, according to Hall measurements. The use of graded buffer technology allows us to vary the indium concentration in the thin channel layer by around 20 percent, without penalizing the material quality. This has enabled us to produce In0.40Ga0.60As channel devices with Hall mobilities exceeding 7000 cm2 V-1 s-1. Being able to tune the composition is highly desirable, because it enables us to balance our device's breakdown voltage and cut-off frequency.
The performance of our InGaAs MOS-HEMTs can now approach that of GaAs pHEMTs and mHEMTs, following optimisation of the gate-stack modules and the ohmic contact, which is based on tungsten and molybdenum. Benchmarking effective mobility for our MOS-HEMTs against that of InGaAs MOSFETs with surface and buried channels reveals that our device has one of the best values for a transistor formed on silicon, thanks to its optimised energy barrier and gate-stack layers (see Figure 7(a)). This mobility, combined with a source resistance as low as 300 Wà—mm, gives a high transconductance of 560 mS/mm for a device with channel length of 0.33 mm (see Figure 7 (b)). The current gain cut-off frequency for our devices is 60 GHz, extracted for transistors with 150 nm gate lengths.
Figure 7. (a) Reported effective mobility (μeff) as a function of effective oxide thickness (EOT) at sheet electron density (Ns) of 3 à—1012 cm-2 for InxGa1-xAs (x ≤0.53) channel MOSFETs fabricated on silicon, GaAs, and InP substrates. The μeff in the MOS-HEMT produced at LEES is among the highest reported for InGaAs MOSFETs on large area silicon substrates. Note that triangles represent buried-channel MOSFETs and squares surface-channel MOSFETs. (b) Peak transconductance (Gm) as a function of channel length (LCH) for GaAs mHEMTs, pHEMTs, and LEES' MOS-HEMTs on silicon. As a result of high III-V material quality, LEES' MOS-HEMTs on silicon can achieve a transconductance that approaches that of GaAs HEMTs on native GaAs substrates at similar channel length. Note that mHEMTs and pHEMTs refer to metamorphic and pseudomorphic HEMTs, respectively.
We are now working on optimizing the millimetrewave power and noise performance of our devices, and developing hybrid circuit technologies for future communication systems.
