Thinner is cooler for GaN devices
GaN transistors promise higher power densities and can operate under higher temperatures (~ 500degC) than conventional silicon transistors, but like all semiconductors they also generate excess heat that can limit their performance.
Cooling methods based on heat sinks and fans add cost and bulk. Now a team of University of Illinois researchers from the University of Illinois Micro + Nanotechnology Lab has created a new method which they say is simple and cost effective.
Using computer aided design, Can Bayram's group has demonstrated that the thickness of GaN layers plays a role in overheating, influencing the device's thermal budget and ultimately its performance.
"Thinner is cooler," said Bayram, adding that conventional GaN transistors are deposited on thick substrates (e.g. silicon, SiC) that are not ideal thermal conductors. Bayram noted the challenges in mismatched epitaxy of GaN on conventional substrates, leading to tens-, and in most cases, hundreds- of microns-thick devices.
"That is really bad for heat dissipation, considering the heat source is scaled down with the gate, in the sub-micron order," said Bayram. Using novel semiconductor release methods such as smart-cut and spalling, one can release the GaN transistor from the rest of the epitaxy and hence from the thick substrates so as to reap the benefits of improved thermal management.
"By thinning the device layer, one can reduce the hotspot temperature of a high-power GaN transistor by about 50degC." said Bayram.
According to graduate student Kihoon Park, who led the research study, there's a limit to the device thinness. "If you reduce it too much, you'd get the inverse effect and actually increase the temperature inside the device," Park said. The optimum thickness turns out to be around a micron or so for typical devices.
This work is significant, they say, because it provides thermal management design guidelines for GaN-based transistors. The optimal layer size is tied to the device's thermal boundary resistance (TBR), which is a condition that exists at the very interface of GaN and other epitaxial layers.
"We determined the optimum layer thicknesses minimising the GaN transistor hot spot temperature considering various values of TBR," said Park. "Also, the layer size depends on how the device will be used. If it's for higher power applications, then you'd want thinner, sub- micron thick-layers, ideally."
The next step for the Illinois team is to study the electrical properties of the GaN layers before actually making GaN transistors on substrates like engineered diamond or epitaxial graphene.
This Illinois research was supported by the Young Investigator Program Grant No. FA9550-16-1-0224 of the Air Force Office of Scientific Research (AFOSR); the results were published in Applied Physics Letters [B1] on October 10, 2016.
'Thermal resistance optimization of GaN/substrate stacks considering thermal boundary resistance and temperature-dependent thermal conductivity', by K. Park and C. Bayram; Appl. Phys. Lett. 109, 151904 (2016);
