
Say hello to the heterogeneous revolution

Recent advances in circuits produced by heterogeneous integration highlight the potential for real world applications.
BY CHRISTOPHER MAXEY, JUSTIN KIM, DAVE HODGE, MARK SOLER, BENNETT COY, DAN GREEN, JAMES BUCKWALTER AND FLORIAN HERRAULT FROM PSEUDOLITHIC INC.
Since the advent of VLSI silicon CMOS, this technology’s RF and millimetre-wave performance has taken a back seat during the inexorable drive towards smaller gate dimensions and higher device density. Stepping up to fill this gap have been a number of compound semiconductors, such as GaAs, GaN, and InP, providing high gain and high output powers at ever higher frequencies. Thanks to these devices, it has been possible to construct solid-state phased-array radars, 5G/6G base-stations and quantum computers. However, these applications pay a significant price in an ecosystem where many may see ‘exotic’ materials as an issue that slows and restricts adoption. Compared to silicon CMOS, it typically takes twice as long to fabricate compound semiconductor devices, which are 5 to 10 times as expensive per unit area, because they lack the fundamental economic benefits of high-volume manufacturing.
Figure 1. Silicon CMOS and compound semiconductors provide unique benefits, while heterogeneous integration promises to deliver the best of both worlds.
One attractive solution to addressing this issue is heterogeneous integration. Many are now investigating this approach that combines the disparate benefits of multiple technologies into a single integrated circuit (see Figure 1). Here, we review the rise in interest in heterogeneous integration, its progress in the context of the historical evolution of semiconductor technologies, and the potential inflection it offers to accelerate deployment of new devices into the marketplace. We also describe the contribution that our company, PseudolithIC, is making – we are the pioneers of a number of ‘first-ever’ prototype designs, including the world’s first millimetre-wave amplifier based on InP and GaN devices.
HI primed for impact
Evidence of accelerating interest in heterogeneous integration is found in increases in journal articles and patent filings over the last three decades (see Figure 2). At the turn of the millennium heterogeneous integration started to take shape as a bone fide topic, and since then there has been a steady rise in publications continuing to the present day. Alongside this trend, there has been a multiplication in both the number of potential approaches to realising integrated solutions, and the potential applications for heterogeneous integration. For example, integration of varying digitally focused chiplets has spawned multiple conferences and consortia, including the recent Universal Chiplet Interconnect Express consortium. Supporting and spurring on much of this activity are federally funded efforts, such as the DARPA CHIPS programme. There are also many efforts driven by government research programmes that focus on mixing optical technologies at the chip scale to trim the cost and improve the performance of photonic integrated circuits.
Figure 2. Articles and patents referencing heterogeneous integration over five-year periods spanning the 1970s to today. The final period includes a linear extrapolation for the remainder of the current period (courtesy Google Scholar).
Looking more broadly at the history of semiconductor innovation, the timeline from a technology’s first results to its commercial deployment has consistently been on the order of two decades. The time that it takes to develop a compound semiconductor device technology, such as that based on GaAs or GaN, is very similar to that for silicon (see Figure 3), with initial device results preceding deployment in commercial applications by about 20 years.
For both GaAs and GaN, development has been facilitated by significant industrial investment, underwritten in part by the US Government. Development of GaAs devices has been supported by the DARPA MIMIC programme, while advances in GaN have been aided by the DARPA WBGS programme. Heterogeneous integration is now on the cusp of commercial employment, and has benefitted from similar developmental investment. Based on historic rates of progress, we can conclude that heterogeneous integration is primed to realise its commercial impact.
Merits of the PseudolithIC approach
A number of research groups are focusing on RF applications, and exploring several approaches. We are involved in this area, but taking the technology much further, by commercialising a chip-scale 2.5D integration approach that leverages existing RF silicon and compound semiconductor ecosystems.
Our approach offers three critical value propositions over monolithic processes, which concentrate on a single material. First, we accelerate the design and fabrication process for a high-performance RF circuit. An example of this is designing new circuits and integrating exotic materials, such as N-polar GaN, faster than a traditional foundry, because we just require chiplets of the material, rather than an entire MMIC. Consequently, several thousand chiplets can be procured from a single tape-out (see Figure 4). Once we have sourced our chiplets and built up an inventory, our designers only need to design the interposer to produce a new pseudolithic IC, which we refer to as simply a PLIC. Second, our approach enables a true ‘mix-and-match’ of different devices, such as InP and GaN, in a single PLIC. This enables optimal architectures that are free from multi-chip modules. Finally, as the interposer is built on wafers with a diameter of at least 8 inches, they have at least four times the area of the 4-inch wafers used in typical III-V processes, leading to significant fab throughput and cost advantages.
To enjoy all these benefits, we employ an approach that begins by sourcing individual active III-V transistors – or even more complex integrated circuits – from either an established defence industrial base or a commercial foundry. After dicing these devices into singulated ‘chiplets’, they are embedded into a separately designed and fabricated silicon substrate interposer, which may feature passive networks, such as transformers, and active CMOS control circuity. By adopting a low-temperature process, we maintain the integrity of the chiplets and the in-situ CMOS devices. Our final step, completing integration at the wafer scale, is the fabrication of copper coplanar waveguide interconnects between the chiplet and interposer.