Hybrid PICs Target Communication Networks Of Tomorrow
Uniting III-Vs with silicon CMOS enables the fabrication of ground-breaking, low-cost lasers for access/metropolitan networks and datacentres by David Carrara and Guang-Hua Duan from III-V Lab and Segolene Oliver from CEA LETI
The last decade has witnessed an explosion in bandwidth demand on telecommunication and data communication networks. This has been driven by an uptake in smartphones, and the introduction of online services such as Youtube, Netflix, Google and Facebook. But this is just the beginning: 4k and 8k video streaming are the emerging new standards; data traffic for the smartphone will soon exceed that for the computer; and due to the growth of the Internet-of-Things, more objects are going to be connected to one another. Given this shift in the landscape, it is clear that bandwidth demands are going to increase drastically over the coming years, straining different layers within the communication networks.
Two of the key segments in this infrastructure are the datacentre and the access/metropolitan networks. The former deals with the data we ‘consume’ from all over the world, while the latter provides links that allow us to access all that data from our homes and offices. In addition, access/metropolitan networks enable data transmission within a city or a local region.
Both the datacentre and the access/metropolitan networks are very different from long haul networks. They are much more sensitive to the cost, and the photonic components that are adopted have to be manufactured in far higher volumes.
To address this pair of requirements, the III-V Lab in Palaiseau, in partnership with CEA Leti in Grenoble, has developed a wafer-bonding approach that can form low-cost, efficient photonic integrated circuits (PICs) by uniting high-performance III-Vs with mature CMOS silicon. Armed with that approach for enabling the bonding of various types of III-V wafers on silicon, we have produced lasers that set a new benchmark for tunability and spectral purity, and fabricated the first silicon Mach Zehnder Modulator that is integrated with a tunable hybrid III-V/silicon laser.
Marrying two materials
At the heart of our approach is the marriage of the two main platforms in the semiconductor industry: silicon and III-V.
The former, the ‘mother’ of modern electronics, is renowned for its really low cost, allied to it suitability for very large-volume production. But there is more to it than just that: silicon, working in tandem with its native oxide, can form compact passive optical elements with very good optical performances. Even modulators and detectors can be directly fabricated within this platform. However, one key component remains elusive – the laser.
Production of the laser is routine with a III-V semiconductor platform – and this can also be used to manufacture high-performance light detectors, modulators and amplifiers. However, these components have high production costs, due to smaller volumes within this industry and the less mature processes it employs.
By exploiting the advantages of both platforms, we have developed a hybrid technology that could unlock the door to the manufacture of low-cost, very high-performance PICs in high volume.
Device fabrication begins by taking 200 mm SOI wafers with a silicon top layer of typically 440 nm and using a hard mask technique to define different waveguide levels. A first partial etch of 220 nm, using a combination of deep UV lithography at 193 nm and reactive ion-etching, forms rib waveguides that are optimized for coupling with III-V waveguides – they are aligned on top of the silicon waveguides in a latter step. Additional etching steps form the passive circuitry, which includes strip waveguides, Bragg reflectors, filters and vertical-output couplers.
After physical structures were defined, selective dopant implantation creates p-n and p-i-n junctions in silicon and germanium. Finally, a high density plasma deposition process encapsulates the surface with an oxide. This oxide is planarized with a chemical-mechanical process to ensure a flat, smooth interface – a pre-requisite for a good molecular bonding with the III-V wafer. In parallel, we grow inverted III-V heterostructures on III-V substrates that have a diameter of either 2-inch, 3-inch or 4-inch. Optimised growth conditions ensure a defect-free surface that enables good quality wafer bonding and ultimately a high performance from the laser.
When working with InP-based semiconductors, the III-V region of our PICs consists of: a p-doped InGaAs contact layer; a p-doped InP cladding layer; typically six InGaAsP quantum wells, surrounded by two InGaAsP separate confinement heterostructure layers; and an n-doped InP layer. Molecular bonding unites these III-V wafers, epitaxial layer down, to the processed SOI wafers. Subsequent wet etching removes the III-V substrate, prior to laser dicing around the III-V wafers. This yields smaller wafers that are easier to process in a III-V fabrication plant.
Figure 1. The different steps used in the hybrid III-V/silicon process.
To define the different active sections of our III-V structure, we employ a combination of UV photolithography at 402 nm, selective wet etching, and reactive-ion etching with a mixture of hydrogen gas and methane (see Figure 1). Electrical contact pads and resistors are added by photolithography, followed by evaporation and sputtering of metals. After this we spin-coat a passivation layer of BCB, and then deposit a second metallic layer – an alloy of titanium, platinum and gold – to access the electrical pads through etched vias. Electro-optic characterisation of these components may be carried out directly on wafer, using the integrated vertical-grating couplers etched directly on the SOI wafers (see Figure 2).