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This article was originally featured in the edition: Volume 24 Issue 6

Showcasing The Compounds At VLSI

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Compound semiconductor highlights at this year's VLSI included tunnel FETs with a record-breaking subthreshold swing, GeSn transistors with a fin width below 10 nm, and InGaAs photoFETs setting a new benchmark for responsivity Richard Stevenson reports

For a decade or more, our community has devoted much effort to the development of III-V transistors for maintaining the march of Moore's Law. It has been argued that armed with a superior mobility to silicon devices, those made from compound semiconductors can operate at a lower voltage while maintaining current, and thus enable power scaling at future nodes.

Progress of these devices is continuing, with some of the latest breakthroughs reported at the 2018 Symposium on VLSI Technology and Circuits, held in late June in Honolulu, HI. At that gathering, where there were also reports of progress associated with III-V photodetectors, highlights included talks on: tunnel FETs made from InGaAs and GaAsSb with a sub-threshold swing that broke new ground; GeSn FinFETs with a fin width below 10 nm that set a new benchmark for transconductance; and tuneable InGaAs nanomenbrane photoFETs on flexible substrates, which are promising for lightweight, wide-angle imaging applications.

Superior sub-threshold swing

Makers of these record-breaking tunnel FETs, Alireza Alian and co-workers from imec, Belgium, claim that their best devices, which sport a vertical nanowire architecture, produce a record transconductance of just 47 mV/decade. This low value is important, because it allows the device to operate at a lower power supply voltage while still delivering a high current. For imec's leading FETs, the drive current is 700 μA/μm at 0.35 V, for a fixed off-current of 1 nA/μm. That voltage is far lower than that used in today's ICs, which operate at around 0.9 V, highlighting the promise of III-V tunnel FETs for all mobile applications, where they could lengthen battery life.

imec's best results were obtained with nanowires with a 30 nm diameter. For insertion in a future node they would need to be "somewhere around ten nanometres", says Alian.



Another group in Europe, based at Lund University, have also produced encouraging results with vertical nanowire devices. "They did it using grown wires," says Alian. "We got quite similar results by etching the wires."

In Alian's view, the top-down approach that he and his co-workers adopt is better suited to high-volume manufacture. "It is believed to be more controllable "“ and less variability is expected than when you grow the wires."

Fabrication of imec's tunnel FETs begins with the growth of III-V layers on an InP substrate. The researchers employ this growth process, rather than MOCVD, because they believe it produces better interfaces. "CVD is usually at a higher temperature than MBE, so intermixing at interfaces is more severe," argues Alain.

The team produced a range of tunnel FETs, formed from nanowires with diameters of either 30 nm, 50 nm, 70 nm or 90 nm. Electron beam lithography defines their diameter, prior to etching into the heterostructure at 100 °C with a methane-based plasma to create these structures. Atomic layer deposition adds a gate oxide, comprising 1 nm-thick Al2O3 and 2 nm-thick HfO2. Fabrication finishes with the addition of a top spacer, top and back contacts, and in some cases an anneal in forming gas at 350 °C (see Figure 1 for a device architecture).



Figure 1. Formation of imec's tunnel FET begins with the growth of a heterostructure by MBE, and the use of lithography to define the diameter of the nanowires (a). Dry etching forms the nanowires (b), before a gate stack is added by atomic layer deposition (c), and a top spacer and top and back contacts are introduced (d).

Measurements on various devices, which have been studied with several microscopy techniques (see Figure 2), reveal significant variations in the drive current and the threshold voltage for transistors with the same nanowire diameter. These variations, which could be addressed by optimising the process, are attributed to unintended differences in doping and nanowire diameter.

Alian and co-workers observed a negative differential resistance in the output characteristics of their transistors, confirming that device behaviour is dominated by tunnelling. Performance improves with annealing in the forming gas, thanks to a reduction in the density of interface traps in the InGaAs layer.

A sub-threshold voltage below 60 mV/decade is only observed in devices with a nanowire diameter of 30 nm and 50 nm. This suggests that narrower wires improve sub-threshold voltage, a conjecture backed by simulations of the band-to-band tunnelling current "“ they indicate that shrinking the nanowire diameter to 20 nm could decrease the subthreshold swing to 20-30 mV/decade.

Any shrinking of the diameter of the nanowires must go hand-in-hand with increases in the source doping and a reduction in gate-source overlap. "Achievinghigher doping is not difficult," says Alian, who believes that it is easy to realise levels of 5 x 1019 cm-3. "For the overlap, it is possible, but variability is expected to become an issue." However, this can be addressed by engineering.

Alian and co-workers are hoping to now investigate the effects of higher doping. After this, the team may go on to study devices with narrower diameters.

Very fine fins

A claim for record-breaking miniaturisation came from a partnership between the National University of Singapore, Nanyang Technological University and Applied Materials. This collaboration believes that it has broken new ground by making GeSn pFETs with a fin width below 10 nm. The width at the top of the fin, produced on a 200 nm GeSn-on-insulator substrate, is just 5 nm.