Strain mitigation improves GaN HEMT performance
Researchers at the Institute of Novel Semiconductors, Shandong University, China, have improved GaN HEMT performance by mitigating local strain concentration at the cap/barrier interface. They reported their findings in Applied Physics Letters.
By inserting a 3 nm AlN sub-cap beneath crystalline SiN, they improved interface quality and reduced interface trap density, enabling higher electron mobility, lower on-resistance and improved threshold-voltage stability.
They say the approach could benefit GaN transistors by mitigating local strain and reducing interface trap density. These improvements can enhance electron transport and help stabilise the threshold voltage under temperature variation and gate-bias stress.
Crystalline SiN caps offer attractive interface properties, but lattice mismatch with the AlGaN barrier can concentrate strain locally. The AlN sub-cap reduces the mismatch at the SiN interface and weakens the compressive influence of the cap on the AlGaN barrier. This redistributes local strain while preserving the coherently strained AlGaN/GaN heterointerface.
The team compared SiN-cap, SiN/GaN-cap and SiN/AlN-cap devices on SiC, using nominally 2 nm SiN caps and identical processing. Both sub-cap layers were 3 nm thick. The devices had an 18 nm Al0.2Ga0.8N barrier, 2 μm gate length and 100 μm gate width.
Geometric phase analysis of the STEM images revealed the central effect of the AlN sub-cap: mitigation of local strain concentration (figure 1 above). Compared with the SiN-cap reference, the SiN/AlN-cap structure showed a more uniform strain distribution near the upper AlGaN interface. The thickness of the affected upper AlGaN region decreased from approximately 9.4 nm to 7.5 nm, providing experimental evidence of the localised strain redistribution.
Multi-frequency capacitance–voltage measurements linked this strain redistribution to improved interface quality. The SiN/AlN-cap sample exhibited the lowest interface trap density: 5.77 × 1011–2.32 × 1012 eV−1 cm−2 for trap energies 0.36–0.42 eV below the conduction-band edge.
The device also showed the highest electron mobility, attributed to reduced interface states and weaker scattering of channel electrons. Its on-resistance was 7.14 Ω·mm, compared with 8.62 Ω·mm for the SiN-cap and 9.90 Ω·mm for the SiN/GaN-cap references, reductions of approximately 17 percent and 28 percent, respectively.
Reduced trapping was reflected in improved threshold-voltage stability. The threshold voltage of the SiN/AlN-cap device shifted by only −0.05 V between 25°C and 150°C, corresponding to −0.4 mV/°C. Under a +2 V gate bias, with the drain at 0 V, the drift was approximately 0.02 V after 1000 s.
Further work could explore AlN sub-cap thickness optimisation and longer stress tests to assess how the strain-engineering approach translates to extended device operation.
Pictured above: Figure 1. Experimental evidence of local strain mitigation. HAADF-STEM images and in-plane (εxx) and out-of-plane (εyy) strain maps compare the SiN-cap reference (top) with the SiN/AlN-cap sample (bottom).
