Rethinking GaN on sapphire
A thin GaN-on-sapphire platform with carbon-buffer engineering and an AlGaN back-barrier delivers multi-kilovolt blocking, a low on-resistance and ampere-level currents.
BY ADRIEN BIDAUD, ABDELKHALEK SEFSSAFI, LYES BEN HAMMOU, ETIENNE OKADA, KATIR ZIOUCHE AND FARID MEDJDOUB FROM CNRS-IEMN AND AJIT PARANJPE FROM PRIMA INNOTECH
Wide and ultra-wide bandgap semiconductors are transforming the prospects for efficient power conversion. Within this portfolio, GaN has a number of key strengths. Its high critical electric field and excellent electron transport enable these devices to switch far faster than those based on conventional silicon technology, while handling higher voltages. But there is a concern with this class of power device: what substrate provides the best foundation?
The most common candidate is silicon, which attracts enormous interest, as it is inexpensive and available in large diameters. And another leading contender is SiC, offering outstanding thermal properties, but at a higher material cost.
Often overlooked is yet another mass-produced substrate, sapphire. It tends to be viewed as a platform belonging to the optoelectronics world. That’s understandable: sapphire is a mature, economical substrate for GaN epitaxy, but its relatively low thermal conductivity suggests it is not well-suited to high-power switching.
However, recent work by our team – a partnership between engineers at the Institute of Electronics, Microelectronics and Nanotechnology in Lille, France, and Prima Innotech – suggests that this judgement is too simplistic. Rather than asking whether sapphire is the perfect substrate in every respect, we have asked a different question: how good can the high-voltage performance from a thin GaN-on-sapphire stack be when the buffer, channel confinement and electric field are deliberately engineered together?
The answer is both surprising and encouraging. We have discovered that field-plate-free lateral HEMTs on thin GaN-on-sapphire structures can deliver blocking voltages as high as 5.5 kV, while preserving a competitive specific on-resistance and scaling to high currents. While these results don’t remove sapphire’s thermal limitation, they show that this must not be confused with an inability to support excellent electrical performance.
Revisiting sapphire
There are a number of good reasons to take another look at sapphire. Following decades of LED manufacturing, GaN-on-sapphire has a mature epitaxial ecosystem based on a relatively inexpensive substrate. Thanks to this infrastructure, high-quality GaN layers can be grown on a platform already established for large-scale compound semiconductor manufacturing.
Figure 1. Epitaxial stack engineering investigates the effects of channel thickness, AlGaN back barrier, and buffer design.
The usual objection is heat. As sapphire’s thermal conductivity is only about 40 W m-1 K-1 – so far below that of SiC – there’s the threat that a GaN device that dissipates substantial power will experience a higher channel temperature. As this is a genuine concern for high-current power transistors, any realistic GaN-on-sapphire roadmap must address this issue, rather than ignore it.
But the thermal conductivity is not the only property determining the usefulness of a power platform. Device designers also consider blocking voltage, leakage, on-resistance, dynamic behaviour, manufacturability, and ultimately the possibility of integrating the active layers with another heat-spreading material. Due to this, our approach is to consider two separate questions, often bundled together: can sapphire support a very strong GaN power device electrically, and if so, how should one manage its thermal weakness?
Thin by design
Conventional routes to realising higher blocking voltages in lateral GaN transistors often rely on lengthening gate-to-drain distances, adding thicker buffers and introducing field plates. These three levers can be effective, but each carries a penalty. Extending the access region increases resistance; thicker buffers require more epitaxial material, potentially increasing growth time and mechanical stress; and field plates help to redistribute the electric field, but at the price of additional capacitance and process complexity.
Due to these drawbacks, we wanted to discover how far we could go without extra electrostatic hardware. So, we avoided field plates when investigating whether variations in the gate-to-drain distance are a good way to realise voltage scaling. With this simple geometry, incorporating a gate length of 2 µm, the emphasis is on the epitaxial stack.
Our optimised structure contains a 20 nm-thick AlGaN barrier, a 150 nm-thick unintentionally doped GaN channel, a 100 nm-thick Al0.06Ga0.94N back-barrier and a carbon-doped GaN buffer that’s just 0.5 µm-thick. The carbon concentration in this high-resistivity buffer is around 1 × 10¹⁹ cm-3.
Crucially, a stack that’s suitable for blocking high voltages does not destroy the transport properties of the channel. According to Hall measurements, our heterostructure has a sheet carrier density of about 8.6 x 10¹² cm-2, an electron mobility close to 1800 cm² V-1 s-1, and a corresponding sheet resistance of roughly 400 ohms per square. These values, indicative of a high-quality two-dimensional electron gas, show we have a low-resistance foundation for efforts directed at blocking several kilovolts.
Shaping the field
In our devices, the two key epilayers below the channel perform different tasks. The carbon-compensated GaN buffer plays a significant role in suppressing the off-state leakage and delaying vertical punch-through, while the AlGaN back-barrier raises the conduction band below the channel, improving electron confinement and reducing spillover into the buffer.
Figure 2. Off-state blocking, showing how buffer insulation and back-barrier confinement shape leakage behaviour.
Our investigations, involving experimental work and simulations based on technology computer-aided design, highlight the contributions of various layers.
We have shown that an increase in the carbon concentration has the strongest impact on blocking capability. Simulations show that raising the carbon concentration in our 0.5 µm-thick buffer from 1 x 10¹⁷ cm-3 to 1 x 10¹⁹ cm-3 strongly redistributes the electric field beneath the gate. When blocking 1 kV, the calculated peak field in the GaN region falls from around 3.2 MV cm-1 to about 1.8 MV cm-1.
While the back-barrier has a more modest direct impact on breakdown voltage, it has a pronounced influence on confinement and leakage behaviour. That’s crucial, because simply increasing compensation in the buffer is not enough: the channel must remain well controlled when the drain voltage rises. The best devices combine strong buffer insulation with good vertical confinement.
Our multi-faceted approach is the central message of our work. What we show is that a high blocking voltage does not have to come from a brute-force increase in epitaxial thickness or ever more elaborate field plates – it may also stem from shaping where the electric field and the carriers are allowed to go.
Five kilovolts
The payoff of our approach is easy to see when we increase the gate-to-drain spacing. When extending this to 40 µm, our optimised field-plate-free transistor blocks 5.5 kV. This corresponds to an average lateral electric field of about 1.4 MV cm-1 over the gate-drain region.
As expected, increasing the gap between the gate and drain leads to a higher on-resistance, because electrons have farther to travel through the access region. However, the specific on-resistance remains competitive, at around 15 mΩ cm² at the longest spacing. This value, combined with the measured breakdown voltage, yields a Baliga figure of merit above 2 GW cm-2 – that’s a useful measure of how effectively a power device combines high-voltage blocking with low conduction loss.
Note that this combination is more important than simply having a high breakdown voltage. Devices that block impressive voltages, but pay for this with excessive resistance, are of limited practical interest. When benchmarking our devices against other reported GaN-on-sapphire devices, as well as GaN devices on silicon and SiC and selected vertical structures, we find that they have a very competitive combination of specific on-resistance and breakdown voltage.
We must emphasise that our voltages are obtained without a field plate. That’s not to say that field plates are undesirable; they remain powerful design tools. But demonstrating a blocking voltage of 5.5 kV without them shows that it is possible to transfer much of the electric-field management to epitaxial design. This equips future device engineers with the freedom to decide whether additional field shaping is worth the accompanying parasitic capacitance and extra fabrication steps.
Figure 3. Electric-field engineering in the buffer. Technology computer-aided design maps at a drain bias of 1 kV show that increasing the carbon concentration from 1 × 10¹⁷ cm-3 to 1 × 10¹⁹ cm-3 substantially reduces the peak electric field beneath the gate.
Scaling current
If a high-voltage unit cell is to be useful, it must be scaled to meaningful current delivery. Due to this, we fabricated multi-finger transistors using the same basic architecture. They include a representative device with 20 gate fingers, each 500 µm wide, that has a total gate periphery of 10 mm and a gate-drain spacing of 30 µm. Measured output characteristics show that, as expected, current increases with the number of fingers. Our 20-finger device delivers close to 3 A under pulsed operation, with scaling remaining close to that expected from smaller structures within the measured range.
Scaling is an important demonstration for sapphire. This platform has often been associated with small devices and moderate power levels, partly due to its thermal reputation. While the realisation of ampere-level currents does not by itself solve thermal management, it verifies that it’s possible to transfer the high-voltage epitaxial concept from small test structures to substantially wider transistors without suffering an electrical scaling penalty within the measured operating range.
Dynamic questions
Static performance is only part of the story for GaN. If charge trapping takes place, this can raise the dynamic on-resistance after an off-state voltage stress, making a device that looks excellent on a conventional current-voltage curve a disappointment during switching.
Our first set of drain-current-transient measurements is encouraging, but must be interpreted carefully. After a 1 s trapping condition at a drain voltage of 20 V, the fall in measured current is only a few percent, and recovery is relatively rapid. So, we do not observe severe current collapse under our preliminary low-stress conditions.
What we are not claiming from these results is that we have dynamic stability under multi-kilovolt stress. High-voltage trapping remains a principal issue we must investigate and optimise. For us, that distinction is important: while a static 5.5 kV result is established, dynamic behaviour at comparable electric fields is still a next step.
Figure 4. Multi-finger design and output current-voltage characteristics demonstrating current scaling to ampere-level operation.
Beyond sapphire
The remaining challenge brings us back to the objection hounding sapphire from the outset: heat. If an active GaN stack delivers excellent electrical performance, does sapphire have to remain underneath it for the entire life of the device?
Not necessarily. One route we are exploring is to use sapphire for what it does well – supporting mature, cost-effective GaN epitaxy – before separating this substrate from the thin active stack, which would be bonded to a more thermally conductive host, such as bulk AlN or a SiC-based carrier. In that architecture the growth substrate and the foundation for the final device don’t have to be the same material.
We are also considering a second, longer-term route, offering a more favourable thermal path: the direct growth of our optimised thin HEMT stack on an engineered substrate. This approach avoids a transfer step, but places more stringent demands on epitaxial compatibility and material quality.
Both our solutions offer new ways to think about the substrate problem. Rather than searching for one material that simultaneously provides low cost, mature epitaxy, excellent electrical isolation and exceptional thermal conductivity, we are backing heterogeneous integration, which allows those functions to be separated.
Ultimately, this message may be the most important implication of our GaN-on-sapphire results. We are not advocating that sapphire should underpin every GaN power substrate, and our present devices do not remove the need for high-voltage dynamic and thermal validation. But they do show that sapphire can support a remarkably strong electrical platform, so long as the epitaxial stack is designed around its properties, rather than despite them.
Based on our encouraging results – a blocking voltage of 5.5 kV, a Baliga figure of merit exceeding 2 GW cm-2, current scaling close to 3 A, and a simple field-plate-free architecture – the case for revisiting GaN-on-sapphire is stronger than ever.
What’s needed next is to preserve those advantages while engineering away the remaining thermal and dynamic constraints. If there’s success on this front, there is a strong case to be made that the mature substrate that helped establish the GaN LED industry should find a second major role, serving in the high-voltage power electronics industry.
