AmberWave and Aixtron to develop CVD equipment for SiGe and strained Si
The three year worldwide license allows Aixtron access to Amberwave’s technology to continue the development of both single and multiwafer strained silicon epitaxy equipment. Aixtron has installed two AIX 2600G3 systems at AmberWave’s New Hampshire R&D facility to facilitate basic research into SiGe on 150 and 200 mm Si substrates. AmberWave operates on a fabless model that will leverage royalties from design teams licensing its intellectual property to fabricate chips.
“This agreement is another step towards bringing SiGe technology to the mainstream,” said Mark Wolf, CEO of AmberWave. Working with Aixtron to optimize their equipment will allow us to provide the industry with the lowest cost solution for strained silicon.”
AmberWave creates strained-silicon MOSFET circuits by growing a graded layer of SiGe several microns thick on a bulk Si wafer. A thin layer of silicon is grown on top of the SiGe buffer. The thin silicon layer is strained as a result of lattice mismatch to the larger SiGe lattice. Electron mobility in the strained silicon is higher than the standard silicon used in CMOS devices. Growth of the graded SiGe layer produces dislocations as the material relaxes to accommodate lattice mismatch during its growth. This relaxation results in a roughened SiGe surface that must be smoothed to provide a planar surface for the growth of a high quality strained Si channel layer. AmberWave has developed a proprietary chemical mechanical polishing (CMP) method to planarize the SiGe surface. Device processing of the strained silicon FETs has the advantage of leveraging standard CMOS processing steps, says the company.
Amberwave says it can also produce high quality Ge surfaces that provide a close lattice match with GaAs using graded buffer layers of SiGe on Si. Grading reduces the effects of dislocation formation resulting from the 4% lattice mismatch between Si and Ge at the Si-SiGe interface. The company has demonstrated GaAs MESFETs and solar cells on Si and was recently awarded a Phase II SBIR grant for GaAs/SiGe/Si optoelectronics development.
In a separate development, Aixtron said it intends to further develop AmberWave’s three-five-on-silicon technology on 300 mm silicon substrates using its Tricent CVD cluster tool. The company says target applications will include HBTs, PHEMTs, MESFETs, LEDs, lasers, detectors and VCSELs.
