Research in several camps suggests that the integration of front-end and baseband components in silicon technology may not be far off, writes Bob Metzger.

As has been pointed out several times in this column, the power-generating capabilities of LDMOS (lateral doubled diffused MOS) transistors make them suitable for cell phone power sources. When used as a power source, these MOS-based devices are typically packaged in a module that is then inserted into the RF front-end, and interfaced to the other front-end RF chips with the liberal use of filters. However, if the LDMOS structure could be integrated with a BiCMOS process, then it would be possible to fabricate an entire phone on a chip, including everything from the RF front-end to the baseband. Merging technologies It has been argued by many that while a phone on a chip would certainly result in a system with an incredibly small footprint, the restrictions imposed by the chosen fabrication technology will inevitably lead to design compromises and performance degradation. However, if a merged LDMOS/CMOS/BJT pro-cess were available, this might offer sufficient design latitude to optimize the individual performance of the various RF and digital portions of the phone. Researchers at the Hong Kong University of Science and Technology and from the Singapore Institute of Microelectronics have reported on just such a merged process, fabricating an LDMOS integrated power amplifier (IPA), including on-chip inductors, to demonstrate the technology s capabilities (Kumar et al.). Figure 1 shows a cross-section of the device. Centered around a 1.5 m CMOS process, the devices were fabricated on a SIMOX substrate with a 190 nm thick silicon layer over a 360 nm buried oxide. Prior to the transistor fabrication, a thick oxide platform for placing the on-chip inductors was formed using a modified LOCOS process. This involves etching a 1.5 m trench on the silicon/buried oxide/silicon substrate and then growing a 3.0 m SiO2 layer. The gate oxide thickness used was 20 nm. After lateral diffusion of the source/ drain implants (these regions also serve as the emitter and sub-collector, respectively, of the lateral BJT), the effective channel length of the LDMOS is 350 nm (this layer also acts as the base of the lateral BJT). Two layers of aluminum are used for metallization and they are separated by an 800 nm layer of low temperature oxide. The top metal layer is 3.0 m thick and is used in the fabrication of the inductor spiral. Performance The resulting LDMOS devices exhibit a breakdown voltage of 21 V, and an ft and fmax of 4.5 and 4.1 GHz, respectively. The NMOS and PMOS transistors with channel length/width ratios of 1.5 m/5.0 m generate IDsat values of 1.3 mA and 0.8 mA, respectively, and threshold voltages of +0.8 V and 1.2 V, respectively. The lateral BJT exhibits a small signal current gain of 20, and a BVCEO of 6.4 V. For 900 MHz operation, the Q factor of the 7 nH inductors that were fabricated was 5.7. Based on this LDMOS, a two-stage Class E common source IPA was fabricated. All matching components, including the output matching network, were also integrated on chip. Operating with a Vdd of 5 V and a quiescent bias voltage of 3 V, the IPA delivered 200 mW with a gain of 16 dB and a PAE of 49%. Not alone The Hong Kong/Singapore researchers are not the only group pursuing this technology. Researchers at MIT have also recently fabricated an LDMOSFET on SOI, in which an under-source body contact is implemented. This both increases the breakdown voltage and enhances the RF performance (Fiorenza). Using a very similar SOI structure to that of the Hong Kong/Singapore researchers, with 20 nm of silicon on top of a 40 nm buried oxide, the under-source body contact is implemented by inserting a p-layer beneath the n+ source and above the buried oxide. This p-layer is then shorted to the n+ source contact by a shunting metal layer which forms an ohmic contact between the source and the p-layer. This body contact suppresses the kink effect typically seen the I-V characteristics of floating body devices, which often leads to excessive device leakage and premature breakdown. When the body contact is turned on, the breakdown voltage of the LDMOS in the off-state is 25 V. After lateral diffusion, the effective gate-length is reduced to 200 nm and the device exhibits an ft and fmax of 14 and 18 GHz, respectively. Because this process is fully compatible with a CMOS process, this small gate-length LDMOS with its novel body contact could easily be merged with the approach used by the Hong Kong/ Singapore group. This could result in an SOI LDMOS/CMOS/BJT process with RF characteristics sufficient to meet the needs of RF applications over the commercially important 0.9 to 2.5 GHz band, opening up the possibility of not only a fully integrated RF front-end, but the potential for the entire radio to be implemented in a single chip. Further reading M Kumar et al. March 2001 IEEE Electron Device Letters 22(3) 136. J G Fiorenza March 2001 IEEE Electron Device Letters 22(3) 136.