UMC gives details of strained silicon process
In a paper at the 2003 VLSI symposium, UMC explained that its strained silicon process exhibited a significant CMOS performance enhancement with over 20% current driving capability successfully demonstrated on a 70 nm strained silicon transistor with a speed enhancement of over 10% on a test circuit.
"UMC’s strained silicon process offers an alternative path to realize performance improvements without aggressive gate length shrinkage," said S W Sun, VP of UMC’s central research and development division.
"We believe that many of our foundry partners will benefit from this enabling technology in the future," added Sun.
UMC is working with AmberWave to enhance p-channel transistor performance, improve strained layer defect density, and decrease substrate-costs associated with this strained silicon technology.
"AmberWave is seeing the interest in strained silicon accelerate significantly as companies look for ways to address the transistor performance challenges associated with deep sub-micron technology." said Mitch Tyson, AmberWave’s CEO.
Tyson says that AmberWave s strong technical know-how and an extensive IP portfolio, can help customers benefit from its strained silicon technology as it moves towards commercial adoption.
"UMC is our early technology partner and we are excited to have collaborated with them to bring the benefits of the strained silicon technology to their foundry partners," said Tyson.
