InP-based transceiver consumes 70% less power
Fujitsu Laboratories in Japan says it has developed a transceiver chipset that uses an InP HEMT for 40Gbps optical communication while consuming less than 1W power – 70% less than conventional technology.
The company says that its multiplexer-demultiplexer chipset actually operates at 50 Gbps. Until now, claims Fujitsu, reducing power consumption without degrading signal quality and operating margins had been a “daunting issue”.
Its new chip architecture generates clock signals with different phases that are used to process data signals. This is said to ensure superior signal quality without the need for a phase-control circuit.
Eliminating the phase-control circuit normally required reduces the chipset power consumption, explained Fujitsu.
The chipset also features a new voltage distribution design, which has reduced the required supply voltage to 1.5V – less than half that normally needed.
”Our new technology delivers high speeds and superior signal quality while benefiting from low power consumption that is expected of CMOS technology,” said Fujitsu. “The 4:1 multiplexer features the world’s highest-quality signal in terms of jitter – 284 femtoseconds.”
Fujitsu now plans to exploit the technology in 16:1 multiplexers with a 2.5 Gbps interface. Its long-term plan is to develop the devices for terabit-class communication systems.
Details of the chipset are being presented at the 2004 IEEE International Solid-State Circuit Conference, which is taking place in San Francisco this week.
