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Palladium Barrier Cuts Materials Bill

If you develop the right process, a switch from a platinum to a palladium barrier can cut your PHEMT production costs without compromising leakage currents, says Skyworks' Kezia Cheng.

One of silicon s primary strengths is a stable complementary oxide that can form the gates of electronic devices such as MOSFETs. Unfortunately, III-Vs are not blessed with a high-quality equivalent of SiO2. Although there has been recent success with esoteric alternatives such as HfO2, the gates used for manufacturing numerous MESFETs, PHEMTs and so on are metallic structures that form a Schottky barrier contact.



This metallic gate usually consists of three different layers, such as a titanium/platinum/gold sandwich structure. Titanium is the popular choice for the base layer that contacts the semiconductor because it forms a high-quality Schottky junction due to its work function and barrier height characteristics. It also adheres well to the semiconductor, but is let down by its poor electrical conductivity – its bulk resistivity is 4 × 10-5 Ω/cm – so a gold layer is added to address this weakness. However, gold tends to migrate and diffuse through titanium into the device, which degrades performance. So to combat this, a barrier layer is sandwiched between the titanium and gold to prevent diffusion.

Platinum is the common choice for this barrier, but as everybody who s bought a platinum ring would know, it is expensive. What s more, the price for refined material has quadrupled in recent years towards $50 /g. So at Skyworks Solutions we have been developing a gate using palladium. This alternative is only about one-sixth of the cost of platinum and can significantly reduce our transistor s bill of materials, although the process is little different.



Our gates are fabricated with a lift-off approach that is widely used throughout the industry (see figure 1). A photoresist is applied to the wafer, before it is patterned using a mask and photolithography. The exposed film is then developed and a metal film is evaporated onto the patterned wafer, before the remaining photoresist is removed to leave metallic contacts.



The particular process that we use involves a negative-acting chemically-amplified resist. This is activated by a post-exposure bake and then developed. The nature of the exposure and the acid diffusion kinetics creates a re-entrant profile (figure 1f) and the gates formed by evaporation into this structure have cross-sections that are narrower at the top than the bottom (figure 2).



Many of these gates also feature a "foot" at the base of the metal (figure 3a), which contains gold and palladium material overlapping the titanium layer – as shown by transmission electron microscopy and energy-dispersive X-ray analysis (figure 3b). This overlap is highly undesirable because it allows palladium and gold to contact the semiconductor surface, before diffusing into the epilayer when sufficient activation energy is available.

Researchers from Taiwan s Chung-Cheng Institute of Technology and Chang-Gung University have determined that the diffusion mechanism into GaAs is mainly interstitial (the foreign atom is much smaller than those in the lattice, so it can move freely between them), and that palladium transport can occur at low temperatures. This means that the thermal energy associated with the plasma-enhanced chemical-vapor nitride deposition used for passivation and the creation of the capacitor s dielectric layer, which takes place at 250&thinsp°C, is sufficient to drive palladium into the semiconductor. Once diffusion is started, palladium and gold can form ohmic contacts with the semiconductor and create a leakage path (see figure 3 for an example). With our normal process conditions, platinum-based barriers rarely suffer from diffusion-related problems and have a lower leakage current than their palladium equivalents.

The unsuitability of our standard process for forming satisfactory palladium-based barriers has driven us to develop an alternative process based on our production Temescal FCE2700 evaporators. These tools feature a metallic source and target separated by 107 cm and are driven by Simba II 15 kW power supplies.

Due to the diffusion issue, our new process must prevent any gold or palladium from coming into contact with GaAs. This is possible by making the titanium layer larger than the palladium and gold layers through the use of a beam sweep for titanium growth. For this layer, the electron beam is swept across the source and titanium is evaporated from an area instead of a point, which increases the area of the deposited layer.

We have also investigated whether lower deposition rates that cut the metallic atom s arrival energy can improve gate quality. When an atom hits the wafer surface it condenses and loses a fixed amount of energy, known as latent energy, and the remainder governs the atom s mobility. By reducing this deposition rate for gold and palladium and using a beam sweep for just the titanium layer, we minimized the gold and palladium overlap with titanium at the base of the gate metal.

We also looked at the effects of film thickness on gate leakage. Barriers were grown with 20% thicker titanium layers and thinner palladium layers, but this variation produced no measurable reduction in the leakage current.



The improvements produced by our new process are clearly illustrated in the before and after images. Focused ion beam/scanning electron microscope images reveal that the existing process produces palladium and gold at the foot of the metal stack and suggest that there is some palladium diffusion (figure 4a). After optimization both of these blemishes are absent (figure 4b). More important, the subsequent thermal treatment applied to the wafer does not drive any diffusion of palladium or gold into the GaAs surface.



The higher quality of our new gates is confirmed by DC process control monitoring tests that compare the performance of our palladium-based gates produced with both processes, using the same mask (see table). At a standard deposition rate the average (mean) gate leakage was cut from 14.3 to 8.2 µA and the standard deviation narrowed from 8.2 to 3.9 µA. Slowing the growth rate also brought significant dividends for both processes and reduced the gate leakage for the optimized process to 4.3 µA. The other key parameters for the device, such as the source-drain current and insertion loss, were unaffected by the new process that delivered a 15% increase in yield compared to the standard process with a palladium-based barrier.

We are now using the palladium-based barrier in production, which has cut our bill of materials. We are also working to improve our understanding of the process and aim to investigate how the sticking coefficients of the metals play a role in the foot formation. Gold and palladium have sticking coefficients of less than unity, so these atoms can reflect off chamber walls and nearby structures to cause a more pronounced foot, particularly at higher deposition rates. Learning how to reduce this foot should ultimately lead to higher yields and make an even stronger case for the palladium-based barrier.

Further reading

D H Yeh et al. 2007 Jap. J. of Appl. Phys. 46 968.

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